| PDL for FM0+ Version1.0 Peripheral Driverl Library for FM0+

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C:/pdl_v10/common/system_s6e1xx.c
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    00001 /*******************************************************************************
    00002 * Copyright (C) 2013 Spansion LLC. All Rights Reserved.
    00003 *
    00004 * This software is owned and published by:
    00005 * Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
    00006 *
    00007 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
    00008 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
    00009 *
    00010 * This software contains source code for use with Spansion
    00011 * components. This software is licensed by Spansion to be adapted only
    00012 * for use in systems utilizing Spansion components. Spansion shall not be
    00013 * responsible for misuse or illegal use of this software for devices not
    00014 * supported herein.  Spansion is providing this software "AS IS" and will
    00015 * not be responsible for issues arising from incorrect user implementation
    00016 * of the software.
    00017 *
    00018 * SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
    00019 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
    00020 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
    00021 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
    00022 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
    00023 * WARRANTY OF NONINFRINGEMENT.
    00024 * SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
    00025 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
    00026 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
    00027 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
    00028 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
    00029 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
    00030 * SAVINGS OR PROFITS,
    00031 * EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    00032 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
    00033 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
    00034 * FROM, THE SOFTWARE.
    00035 *
    00036 * This software may be replicated in part or whole for the licensed use,
    00037 * with the restriction that this Disclaimer and Copyright notice must be
    00038 * included with each copy of this software, whether used in part or whole,
    00039 * at all times.
    00040 */
    00041 /******************************************************************************/
    00042
    00043 #include "mcu.h"
    00044
    00060 uint32_t SystemCoreClock = __HCLK;
    00061
    00069 void SystemCoreClockUpdate (void) {
    00070   uint32_t masterClk;
    00071   uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
    00072
    00073   switch ((FM0P_CRG->SCM_CTL >> 5U) & 0x07U) {
    00074     case 0u:                                 /* internal High-speed Cr osc.    */
    00075       masterClk = __CLKHC;
    00076       break;
    00077
    00078     case 1u:                                 /* external main osc.             */
    00079       masterClk = __CLKMO;
    00080       break;
    00081
    00082     case 2u:                                 /* PLL clock                      */
    00083   // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
    00084   // violation:
    00085   //   "Unordered accesses to a volatile location"
    00086       u32RegisterRead = (__CLKMO  * (((uint32_t)(FM0P_CRG->PLL_CTL2) & 0x1Fu) + 1u));
    00087       masterClk = (u32RegisterRead / ((((uint32_t)(FM0P_CRG->PLL_CTL1) >> 4ul) & 0x0Fu) + 1u));
    00088       break;
    00089
    00090     case 4u:                                 /* internal Low-speed CR osc.     */
    00091       masterClk = __CLKLC;
    00092       break;
    00093
    00094     case 5u:                                 /* external Sub osc.              */
    00095       masterClk = __CLKSO;
    00096       break;
    00097
    00098     default:
    00099       masterClk = 0ul;
    00100       break;
    00101   }
    00102
    00103   switch (FM0P_CRG->BSC_PSR & 0x07u) {
    00104     case 0u:
    00105       SystemCoreClock = masterClk;
    00106       break;
    00107
    00108     case 1u:
    00109       SystemCoreClock = masterClk / 2u;
    00110       break;
    00111
    00112     case 2u:
    00113       SystemCoreClock = masterClk / 3u;
    00114       break;
    00115
    00116     case 3u:
    00117       SystemCoreClock = masterClk / 4u;
    00118       break;
    00119
    00120     case 4u:
    00121       SystemCoreClock = masterClk / 6u;
    00122       break;
    00123
    00124     case 5u:
    00125       SystemCoreClock = masterClk /8u;
    00126       break;
    00127
    00128     case 6u:
    00129       SystemCoreClock = masterClk /16u;
    00130       break;
    00131
    00132     default:
    00133       SystemCoreClock = 0ul;
    00134       break;
    00135   }
    00136
    00137 }
    00138
    00147 void SystemInit (void) {
    00148
    00149 #if (CLOCK_SETUP == CLOCK_SETTING_CMSIS)
    00150   static uint8_t u8IoRegisterRead;  // Workaround variable for MISRA C rule conformance
    00151 #endif
    00152
    00153 #if (HWWD_DISABLE)                                 /* HW Watchdog Disable */
    00154   FM0P_HWWDT->WDG_LCK = 0x1ACCE551u;                /* HW Watchdog Unlock */
    00155   FM0P_HWWDT->WDG_LCK = 0xE5331AAEu;
    00156   FM0P_HWWDT->WDG_CTL = 0u;                         /* HW Watchdog stop */
    00157 #endif
    00158
    00159 #if (CLOCK_SETUP == CLOCK_SETTING_CMSIS)                     /* Clock Setup */
    00160   FM0P_CRG->BSC_PSR   = (uint8_t)BSC_PSR_Val;                 /* set System Clock presacaler */
    00161   FM0P_CRG->APBC0_PSR = (uint8_t)APBC0_PSR_Val;               /* set APB0 presacaler */
    00162   FM0P_CRG->APBC1_PSR = (uint8_t)APBC1_PSR_Val;               /* set APB1 presacaler */
    00163   FM0P_CRG->SWC_PSR   = (uint8_t)(SWC_PSR_Val | (1ul << 7u)); /* set SW Watchdog presacaler */
    00164
    00165   FM0P_CRG->CSW_TMR   = (uint8_t)CSW_TMR_Val;                 /* set oscillation stabilization wait time */
    00166
    00167   if (SCM_CTL_Val & (1ul << 1u)) {                 /* Main clock oscillator enabled ? */
    00168     FM0P_CRG->SCM_CTL |= (uint8_t)(1ul << 1u);            /* enable main oscillator */
    00169
    00170     while (((FM0P_CRG->SCM_STR) & (uint8_t)(1ul << 1u)) != (uint8_t)(1ul << 1u)) /* wait for Main clock oscillation stable */
    00171     {}
    00172   }
    00173
    00174   if (SCM_CTL_Val & (1ul << 3))                     /* Sub clock oscillator enabled ? */
    00175   {
    00176     FM0P_CRG->SCM_CTL |= (1ul << 3);                // enable sub oscillator
    00177     while ((FM0P_CRG->SCM_STR & (uint8_t)(1ul << 3)) != (uint8_t)(1ul << 3))       // wait for Sub clock oscillation stable
    00178     {}
    00179   }
    00180
    00181   FM0P_CRG->PSW_TMR   =  (uint8_t)PSW_TMR_Val;                // set PLL stabilization wait time
    00182   FM0P_CRG->PLL_CTL1  = (uint8_t) PLL_CTL1_Val;               // set PLLM and PLLK
    00183   FM0P_CRG->PLL_CTL2  =  (uint8_t)PLL_CTL2_Val;               // set PLLN
    00184
    00185   if (SCM_CTL_Val &  (uint8_t)(1ul << 4u)) {                 // PLL enabled?
    00186     FM0P_CRG->SCM_CTL  |=  (uint8_t)(1ul << 4u);              // enable PLL
    00187     while ((FM0P_CRG->SCM_STR &  (uint8_t)(1ul << 4u)) != (uint8_t)(1ul << 4u))      // wait for PLL stable
    00188     {}
    00189
    00190     if (SCM_CTL_Val & (1ul << 1u) == 0u)  // main clock disable, use high-speed CR for PLL
    00191     {
    00192         FM0P_CRG->PSW_TMR_f.PINC = 1u;
    00193     }
    00194   }
    00195
    00196   FM0P_CRG->SCM_CTL  |=  (uint8_t)(SCM_CTL_Val & 0xE0u);       // Set Master Clock switch
    00197
    00198   // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
    00199   // violations:
    00200   //   "Unordered reads and writes to or from same location" and
    00201   //   "Unordered accesses to a volatile location"
    00202   do
    00203   {
    00204     u8IoRegisterRead = (FM0P_CRG->SCM_CTL & 0xE0u);
    00205   }while ((FM0P_CRG->SCM_STR & 0xE0u) != u8IoRegisterRead);
    00206
    00207   if ((SCM_CTL_Val & 1u) != 1u) {             /* High-speed CR oscillator disabled ? */
    00208     FM0P_CRG->SCM_CTL &= (uint8_t)(~1ul);      /* disable High-speed CR oscillator */
    00209   }
    00210
    00211 #elif (CLOCK_SETUP == CLOCK_SETTING_NONE)
    00212
    00213   // user defined clock setting
    00214
    00215 #else
    00216   #error Clock setup type unknown!
    00217 #endif
    00218
    00219 #if (CR_TRIM_SETUP)
    00220   /* CR Trimming Data  */
    00221   if( 0x000003FFu != (FM0P_FLASH_IF->CRTRMM & 0x000003FFu) )
    00222   {
    00223     /* UnLock (MCR_FTRM) */
    00224     FM0P_CRTRIM->MCR_RLR =  (uint32_t)0x1ACCE554u;
    00225     /* Set MCR_FTRM */
    00226     FM0P_CRTRIM->MCR_FTRM = (uint16_t)FM0P_FLASH_IF->CRTRMM;
    00227     /* Set MCR_TTRM */
    00228     FM0P_CRTRIM->MCR_TTRM = (uint16_t)(FM0P_FLASH_IF->CRTRMM >> 16u);
    00229     /* Lock (MCR_FTRM) */
    00230     FM0P_CRTRIM->MCR_RLR =  (uint32_t)0x00000000u;
    00231   }
    00232 #endif // (CR_TRIM_SETUP)
    00233 }
    00234
    00235
    00236