PDL for FM0+  Version1.0
Peripheral Driverl Library for FM0+
C:/pdl_v10/common/system_s6e1xx.c File Reference
#include "mcu.h"
Include dependency graph for system_s6e1xx.c:

Go to the source code of this file.

Functions

void SystemCoreClockUpdate (void)
 Update the System Core Clock with current core Clock retrieved from cpu registers.
void SystemInit (void)
 Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable.

Variables

uint32_t SystemCoreClock = ( ( (( ( 4000000ul ) * ((( 0x00000009ul ) & 0x3Ful) + 1ul) ) / ((( 0x00000001ul >> 4ul) & 0x0Ful) + 1ul) ) ) / 1ul)

Detailed Description

FM0+ system initialization functions All adjustments can be done in belonging header file.

History: 2013-12-09 0.1 Edison Zhang first version for FM0+ s6e1a1 series 2014-03-09 0.2 Edison Zhang Support high speed CR PLL mode

Definition in file system_s6e1xx.c.


Function Documentation

void SystemCoreClockUpdate ( void  )

Update the System Core Clock with current core Clock retrieved from cpu registers.

Parameters:
none
Returns:
none

Definition at line 69 of file system_s6e1xx.c.

References __CLKHC, __CLKLC, __CLKMO, __CLKSO, and SystemCoreClock.

void SystemInit ( void  )

Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable.

Parameters:
none
Returns:
none

Definition at line 147 of file system_s6e1xx.c.

References APBC0_PSR_Val, APBC1_PSR_Val, BSC_PSR_Val, CSW_TMR_Val, PLL_CTL1_Val, PLL_CTL2_Val, PSW_TMR_Val, SCM_CTL_Val, and SWC_PSR_Val.


Variable Documentation

uint32_t SystemCoreClock = ( ( (( ( 4000000ul ) * ((( 0x00000009ul ) & 0x3Ful) + 1ul) ) / ((( 0x00000001ul >> 4ul) & 0x0Ful) + 1ul) ) ) / 1ul)

System Clock Frequency (Core Clock) Variable according CMSIS

Definition at line 60 of file system_s6e1xx.c.

Referenced by At24cxx_Delayms(), At24cxx_RandomRead(), I2cTxRxData(), Mfs_I2c_GenerateRestart(), Mfs_I2c_GenerateStart(), Mfs_I2c_GenerateStop(), and SystemCoreClockUpdate().