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PDL for FM0+
Version1.0
Peripheral Driverl Library for FM0+
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00001 /******************************************************************************* 00002 * Copyright (C) 2013 Spansion LLC. All Rights Reserved. 00003 * 00004 * This software is owned and published by: 00005 * Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). 00006 * 00007 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 00008 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. 00009 * 00010 * This software contains source code for use with Spansion 00011 * components. This software is licensed by Spansion to be adapted only 00012 * for use in systems utilizing Spansion components. Spansion shall not be 00013 * responsible for misuse or illegal use of this software for devices not 00014 * supported herein. Spansion is providing this software "AS IS" and will 00015 * not be responsible for issues arising from incorrect user implementation 00016 * of the software. 00017 * 00018 * SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, 00019 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 00020 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 00021 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 00022 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 00023 * WARRANTY OF NONINFRINGEMENT. 00024 * SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 00025 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 00026 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 00027 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 00028 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 00029 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 00030 * SAVINGS OR PROFITS, 00031 * EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00032 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR 00033 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 00034 * FROM, THE SOFTWARE. 00035 * 00036 * This software may be replicated in part or whole for the licensed use, 00037 * with the restriction that this Disclaimer and Copyright notice must be 00038 * included with each copy of this software, whether used in part or whole, 00039 * at all times. 00040 */ 00041 /******************************************************************************/ 00052 /******************************************************************************/ 00053 /* Include files */ 00054 /******************************************************************************/ 00055 #include "ppg.h" 00056 00057 #if (defined(PDL_PERIPHERAL_PPG_ACTIVE)) 00058 00059 #if (PDL_INTERRUPT_ENABLE_PPG == PDL_ON) 00060 /******************************************************************************/ 00061 /* Static variable definitions */ 00062 /******************************************************************************/ 00063 static func_ptr_t pfnPpgCallback[PPG_INT_MAX_CH]; 00064 00072 static void Ppg_InitNvic(uint8_t u8Ch) 00073 { 00074 if ((u8Ch == PPG_CH0) || (u8Ch == PPG_CH2) || (u8Ch == PPG_CH4) || 00075 (u8Ch == PPG_CH8) || (u8Ch == PPG_CH10) || (u8Ch == PPG_CH12) || 00076 (u8Ch == PPG_CH16) || (u8Ch == PPG_CH18) || (u8Ch == PPG_CH20) ) 00077 { 00078 NVIC_ClearPendingIRQ(PPG_IRQn); 00079 NVIC_EnableIRQ(PPG_IRQn); 00080 NVIC_SetPriority(PPG_IRQn, PDL_IRQ_LEVEL_PPG); 00081 } 00082 } 00083 00091 static void Ppg_DeInitNvic(uint8_t u8Ch) 00092 { 00093 if ((u8Ch == PPG_CH0) || (u8Ch == PPG_CH2) || (u8Ch == PPG_CH4) || 00094 (u8Ch == PPG_CH8) || (u8Ch == PPG_CH10) || (u8Ch == PPG_CH12) || 00095 (u8Ch == PPG_CH16) || (u8Ch == PPG_CH18) || (u8Ch == PPG_CH20) ) 00096 { 00097 if(bFM0P_MFT_PPG_PPGC0_PIE == 1) 00098 { 00099 return; 00100 } 00101 00102 if(bFM0P_MFT_PPG_PPGC2_PIE == 1) 00103 { 00104 return; 00105 } 00106 00107 if(bFM0P_MFT_PPG_PPGC4_PIE == 1) 00108 { 00109 return; 00110 } 00111 00112 if(bFM0P_MFT_PPG_PPGC8_PIE == 1) 00113 { 00114 return; 00115 } 00116 00117 if(bFM0P_MFT_PPG_PPGC10_PIE == 1) 00118 { 00119 return; 00120 } 00121 00122 if(bFM0P_MFT_PPG_PPGC12_PIE == 1) 00123 { 00124 return; 00125 } 00126 00127 if(bFM0P_MFT_PPG_PPGC16_PIE == 1) 00128 { 00129 return; 00130 } 00131 00132 if(bFM0P_MFT_PPG_PPGC18_PIE == 1) 00133 { 00134 return; 00135 } 00136 00137 if(bFM0P_MFT_PPG_PPGC20_PIE == 1) 00138 { 00139 return; 00140 } 00141 00142 NVIC_ClearPendingIRQ(PPG_IRQn); 00143 NVIC_DisableIRQ(PPG_IRQn); 00144 NVIC_SetPriority(PPG_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); 00145 } 00146 } 00147 00152 void Ppg_IrqHandler(void) 00153 { 00154 if(bFM0P_MFT_PPG_PPGC0_PUF == 1) // IRQ triggered by ch.0? 00155 { 00156 bFM0P_MFT_PPG_PPGC0_PUF = 0; 00157 bFM0P_MFT_PPG_PPGC1_PUF = 0; 00158 pfnPpgCallback[0](); 00159 } 00160 00161 if(bFM0P_MFT_PPG_PPGC2_PUF == 1) // IRQ triggered by ch.2? 00162 { 00163 bFM0P_MFT_PPG_PPGC2_PUF = 0; 00164 bFM0P_MFT_PPG_PPGC3_PUF = 0; 00165 pfnPpgCallback[1](); 00166 } 00167 00168 if(bFM0P_MFT_PPG_PPGC4_PUF == 1) // IRQ triggered by ch.4? 00169 { 00170 bFM0P_MFT_PPG_PPGC4_PUF = 0; 00171 bFM0P_MFT_PPG_PPGC5_PUF = 0; 00172 pfnPpgCallback[2](); 00173 } 00174 00175 if(bFM0P_MFT_PPG_PPGC8_PUF == 1) // IRQ triggered by ch.8? 00176 { 00177 bFM0P_MFT_PPG_PPGC8_PUF = 0; 00178 bFM0P_MFT_PPG_PPGC9_PUF = 0; 00179 pfnPpgCallback[3](); 00180 } 00181 00182 if(bFM0P_MFT_PPG_PPGC10_PUF == 1) // IRQ triggered by ch.10? 00183 { 00184 bFM0P_MFT_PPG_PPGC10_PUF = 0; 00185 bFM0P_MFT_PPG_PPGC11_PUF = 0; 00186 pfnPpgCallback[4](); 00187 } 00188 00189 if(bFM0P_MFT_PPG_PPGC12_PUF == 1) // IRQ triggered by ch.12? 00190 { 00191 bFM0P_MFT_PPG_PPGC12_PUF = 0; 00192 bFM0P_MFT_PPG_PPGC13_PUF = 0; 00193 pfnPpgCallback[5](); 00194 } 00195 00196 if(bFM0P_MFT_PPG_PPGC16_PUF == 1) // IRQ triggered by ch.16? 00197 { 00198 bFM0P_MFT_PPG_PPGC16_PUF = 0; 00199 bFM0P_MFT_PPG_PPGC17_PUF = 0; 00200 pfnPpgCallback[6](); 00201 } 00202 00203 if(bFM0P_MFT_PPG_PPGC18_PUF == 1) // IRQ triggered by ch.18? 00204 { 00205 bFM0P_MFT_PPG_PPGC18_PUF = 0; 00206 bFM0P_MFT_PPG_PPGC19_PUF = 0; 00207 pfnPpgCallback[7](); 00208 } 00209 00210 if(bFM0P_MFT_PPG_PPGC20_PUF == 1) // IRQ triggered by ch.20? 00211 { 00212 bFM0P_MFT_PPG_PPGC20_PUF = 0; 00213 bFM0P_MFT_PPG_PPGC21_PUF = 0; 00214 pfnPpgCallback[8](); 00215 } 00216 } 00217 00218 #endif 00219 00235 en_result_t Ppg_Init( uint8_t u8CoupleCh, 00236 stc_ppg_config_t *pstcConfig) 00237 { 00238 volatile uint8_t *pu8Ppgc0Addr, *pu8Ppgc1Addr; 00239 volatile uint16_t *pu8Revc0, *pu8Revc1; 00240 volatile uint8_t *pu8Gatec; 00241 uint8_t u8Offset, u8Gap; 00242 if( ((u8CoupleCh%2) != 0) || 00243 (u8CoupleCh > PPG_COUPLE_CH2223) || 00244 (pstcConfig == NULL) || 00245 (pstcConfig->enEvenClock > PpgPclkDiv64) || 00246 (pstcConfig->enEvenLevel > PpgReverseLevel) || 00247 (pstcConfig->enOddClock > PpgPclkDiv64) || 00248 (pstcConfig->enOddLevel > PpgReverseLevel) || 00249 (pstcConfig->enMode > Ppg16Bit16Pres) ) 00250 { 00251 return ErrorInvalidParameter ; 00252 } 00253 u8Offset = u8CoupleCh%4; 00254 u8Gap = u8CoupleCh/4; 00255 pu8Ppgc1Addr = (uint8_t*)FM0P_MFT_PPG_BASE + 0x200 + u8Gap*0x40 + u8Offset*2; 00256 pu8Ppgc0Addr = (uint8_t*)FM0P_MFT_PPG_BASE + 0x200 + u8Gap*0x40 + u8Offset*2 + 1; 00257 pu8Revc0 = (uint16_t*)((uint8_t*)FM0P_MFT_PPG_BASE + 0x104); 00258 pu8Revc1 = (uint16_t*)((uint8_t*)FM0P_MFT_PPG_BASE + 0x144); 00259 pu8Gatec = (uint8_t*)FM0P_MFT_PPG_BASE + 0x218 + u8Gap*0x40; 00260 // set mode 00261 *pu8Ppgc0Addr &= ~(3ul<<1); 00262 *pu8Ppgc0Addr |= (uint8_t)((uint8_t)pstcConfig->enMode<<1); 00263 // set even channel clock, level 00264 *pu8Ppgc0Addr &= ~(3ul<<3); 00265 *pu8Ppgc0Addr |= (uint8_t)((uint8_t)pstcConfig->enEvenClock<<3); 00266 if(u8CoupleCh < PPG_CH16) 00267 { 00268 *pu8Revc0 &= ~(1ul<<u8CoupleCh); 00269 *pu8Revc0 |= (uint8_t)((uint8_t)pstcConfig->enEvenLevel<<u8CoupleCh); 00270 } 00271 else 00272 { 00273 *pu8Revc1 &= ~(1ul<<(u8CoupleCh-PPG_CH16)); 00274 *pu8Revc1 |= (uint8_t)((uint8_t)pstcConfig->enEvenLevel<<(u8CoupleCh-PPG_CH16)); 00275 } 00276 // set odd channel clock, level 00277 *pu8Ppgc1Addr &= ~(3ul<<3); 00278 *pu8Ppgc1Addr |= (uint8_t)((uint8_t)pstcConfig->enOddClock<<3); 00279 if(u8CoupleCh < PPG_CH16) 00280 { 00281 *pu8Revc0 &= ~(1ul<<u8CoupleCh); 00282 *pu8Revc0 |= (uint8_t)((uint8_t)pstcConfig->enOddLevel<<(u8CoupleCh+1)); 00283 } 00284 else 00285 { 00286 *pu8Revc1 &= ~(1ul<<(u8CoupleCh+1-PPG_CH16)); 00287 *pu8Revc1 |= (uint8_t)((uint8_t)pstcConfig->enOddLevel<<(u8CoupleCh+1-PPG_CH16)); 00288 } 00289 // set PPG mode 00290 switch (pstcConfig->enTrig) 00291 { 00292 case PpgSoftwareTrig: 00293 *pu8Ppgc0Addr &= ~1ul; 00294 if((u8CoupleCh%4) == 0) 00295 { 00296 *pu8Gatec &= ~(1ul<<1); 00297 } 00298 else 00299 { 00300 *pu8Gatec &= ~(1ul<<5); 00301 } 00302 break; 00303 case PpgMftGateTrig: 00304 *pu8Ppgc0Addr &= ~1ul; 00305 if((u8CoupleCh%4) == 0) 00306 { 00307 *pu8Gatec |= (1ul<<1); 00308 } 00309 else 00310 { 00311 *pu8Gatec |= (1ul<<5); 00312 } 00313 break; 00314 case PpgTimingGenTrig: 00315 *pu8Ppgc0Addr |= 1ul; 00316 break; 00317 default: 00318 break; 00319 } 00320 00321 return Ok; 00322 } 00323 00336 en_result_t Ppg_StartSoftwareTrig(uint8_t u8Ch) 00337 { 00338 if((u8Ch > PPG_CH23)) 00339 { 00340 return ErrorInvalidParameter ; 00341 } 00342 00343 if(u8Ch < PPG_CH16) 00344 { 00345 FM0P_MFT_PPG->TRG0 |= (uint16_t)(1ul<<u8Ch); 00346 } 00347 else 00348 { 00349 FM0P_MFT_PPG->TRG1 |= (uint16_t)(1ul<<(u8Ch-PPG_CH16)); 00350 } 00351 00352 return Ok; 00353 } 00354 00367 en_result_t Ppg_StopSoftwareTrig(uint8_t u8Ch) 00368 { 00369 if((u8Ch > PPG_CH23)) 00370 { 00371 return ErrorInvalidParameter ; 00372 } 00373 00374 if(u8Ch < PPG_CH16) 00375 { 00376 FM0P_MFT_PPG->TRG0 &= (uint16_t)(~(1ul<<u8Ch)); 00377 } 00378 else 00379 { 00380 FM0P_MFT_PPG->TRG1 &= (uint16_t)(~(1ul<<(u8Ch-PPG_CH16))); 00381 } 00382 00383 return Ok; 00384 } 00385 00401 en_result_t Ppg_SelGateLevel(uint8_t u8EvenCh, en_ppg_gate_level_t enLevel) 00402 { 00403 volatile uint8_t *pu8Gatec; 00404 if( ((u8EvenCh%2) != 0) || 00405 (u8EvenCh > PPG_CH22) || 00406 (enLevel > PpgGateLowActive) ) 00407 { 00408 return ErrorInvalidParameter ; 00409 } 00410 00411 pu8Gatec = (uint8_t*)FM0P_MFT_PPG_BASE + 0x218 + 0x40*(u8EvenCh/4); 00412 00413 if((u8EvenCh%4) == 0) 00414 { 00415 *pu8Gatec &= ~(1ul); 00416 *pu8Gatec |= enLevel; 00417 } 00418 else 00419 { 00420 *pu8Gatec &= ~(1ul<<4); 00421 *pu8Gatec |= (uint8_t)((uint8_t)enLevel<<4); 00422 } 00423 00424 return Ok; 00425 } 00426 00439 en_result_t Ppg_ConfigUpCnt0(stc_ppg_upcnt0_config_t* pstcConfig) 00440 { 00441 if((pstcConfig != NULL) || 00442 (pstcConfig->enClk > PpgUpCntPclkDiv64 )) 00443 { 00444 return ErrorInvalidParameter ; 00445 } 00446 00447 FM0P_MFT_PPG->TTCR0 &= ~(3ul<<2); 00448 FM0P_MFT_PPG->TTCR0 |= (uint16_t)((uint16_t)pstcConfig->enClk<<2); 00449 FM0P_MFT_PPG->COMP0 = pstcConfig->u8CmpValue0; 00450 FM0P_MFT_PPG->COMP2 = pstcConfig->u8CmpValue2; 00451 FM0P_MFT_PPG->COMP4 = pstcConfig->u8CmpValue4; 00452 FM0P_MFT_PPG->COMP6 = pstcConfig->u8CmpValue6; 00453 return Ok; 00454 } 00455 00460 void Ppg_StartUpCnt0(void) 00461 { 00462 bFM0P_MFT_PPG_TTCR0_STR0 = 1; 00463 } 00464 00473 en_stat_flag_t Ppg_GetUpCnt0Status(void) 00474 { 00475 en_stat_flag_t enRet; 00476 00477 (bFM0P_MFT_PPG_TTCR0_MONI0 == 1) ? (enRet = PdlSet) : (enRet = PdlClr); 00478 00479 return enRet; 00480 } 00481 00494 en_result_t Ppg_DisableTimerGen0StartTrig(stc_timer0_gen_ch_t* pstcTimer0GenCh) 00495 { 00496 if((pstcTimer0GenCh->bPpgCh0 > 1) || 00497 (pstcTimer0GenCh->bPpgCh2 > 1) || 00498 (pstcTimer0GenCh->bPpgCh4 > 1) || 00499 (pstcTimer0GenCh->bPpgCh6 > 1) ) 00500 { 00501 return ErrorInvalidParameter; 00502 } 00503 00504 bFM0P_MFT_PPG_TTCR0_TRG0O = ((pstcTimer0GenCh->bPpgCh0 == 1) ? 1 : 0); 00505 bFM0P_MFT_PPG_TTCR0_TRG2O = ((pstcTimer0GenCh->bPpgCh2 == 1) ? 1 : 0); 00506 bFM0P_MFT_PPG_TTCR0_TRG4O = ((pstcTimer0GenCh->bPpgCh4 == 1) ? 1 : 0); 00507 bFM0P_MFT_PPG_TTCR0_TRG6O = ((pstcTimer0GenCh->bPpgCh6 == 1) ? 1 : 0); 00508 return Ok; 00509 } 00510 00523 en_result_t Ppg_ConfigUpCnt1(stc_ppg_upcnt1_config_t* pstcConfig) 00524 { 00525 if(pstcConfig->enClk > PpgUpCntPclkDiv64 ) 00526 { 00527 return ErrorInvalidParameter ; 00528 } 00529 00530 FM0P_MFT_PPG->TTCR1 &= ~(3ul<<2); 00531 FM0P_MFT_PPG->TTCR1 |= (uint16_t)((uint16_t)pstcConfig->enClk<<2); 00532 FM0P_MFT_PPG->COMP1 = pstcConfig->u8CmpValue8; 00533 FM0P_MFT_PPG->COMP3 = pstcConfig->u8CmpValue10; 00534 FM0P_MFT_PPG->COMP5 = pstcConfig->u8CmpValue12; 00535 FM0P_MFT_PPG->COMP7 = pstcConfig->u8CmpValue14; 00536 return Ok; 00537 } 00538 00543 void Ppg_StartUpCnt1(void) 00544 { 00545 bFM0P_MFT_PPG_TTCR1_STR1 = 1; 00546 } 00547 00556 en_stat_flag_t Ppg_GetUpCnt1Status(void) 00557 { 00558 en_stat_flag_t enRet; 00559 00560 (bFM0P_MFT_PPG_TTCR1_MONI1 == 1) ? (enRet = PdlSet) : (enRet = PdlClr); 00561 00562 return enRet; 00563 } 00564 00577 en_result_t Ppg_DisableTimerGen1StartTrig(stc_timer1_gen_ch_t* pstcTimer1GenCh) 00578 { 00579 if((pstcTimer1GenCh->bPpgCh8 > 1) || 00580 (pstcTimer1GenCh->bPpgCh10 > 1) || 00581 (pstcTimer1GenCh->bPpgCh12 > 1) || 00582 (pstcTimer1GenCh->bPpgCh14 > 1) ) 00583 { 00584 return ErrorInvalidParameter; 00585 } 00586 00587 bFM0P_MFT_PPG_TTCR1_TRG1O = ((pstcTimer1GenCh->bPpgCh8 == 1) ? 1 : 0); 00588 bFM0P_MFT_PPG_TTCR1_TRG3O = ((pstcTimer1GenCh->bPpgCh10 == 1) ? 1 : 0); 00589 bFM0P_MFT_PPG_TTCR1_TRG5O = ((pstcTimer1GenCh->bPpgCh12 == 1) ? 1 : 0); 00590 bFM0P_MFT_PPG_TTCR1_TRG7O = ((pstcTimer1GenCh->bPpgCh14 == 1) ? 1 : 0); 00591 return Ok; 00592 } 00593 00606 en_result_t Ppg_ConfigUpCnt2(stc_ppg_upcnt2_config_t* pstcConfig) 00607 { 00608 if(pstcConfig->enClk > PpgUpCntPclkDiv64 ) 00609 { 00610 return ErrorInvalidParameter ; 00611 } 00612 00613 FM0P_MFT_PPG->TTCR1 &= ~(3ul<<2); 00614 FM0P_MFT_PPG->TTCR1 |= (uint16_t)((uint16_t)pstcConfig->enClk<<2); 00615 FM0P_MFT_PPG->COMP8 = pstcConfig->u8CmpValue16; 00616 FM0P_MFT_PPG->COMP10 = pstcConfig->u8CmpValue18; 00617 FM0P_MFT_PPG->COMP12 = pstcConfig->u8CmpValue20; 00618 FM0P_MFT_PPG->COMP14 = pstcConfig->u8CmpValue22; 00619 return Ok; 00620 } 00621 00626 void Ppg_StartUpCnt2(void) 00627 { 00628 bFM0P_MFT_PPG_TTCR2_STR2 = 1; 00629 } 00630 00639 en_stat_flag_t Ppg_GetUpCnt2Status(void) 00640 { 00641 en_stat_flag_t enRet; 00642 (bFM0P_MFT_PPG_TTCR2_MONI2 == 1) ? (enRet = PdlSet) : (enRet = PdlClr); 00643 return enRet; 00644 } 00645 00658 en_result_t Ppg_DisableTimerGen2StartTrig(stc_timer2_gen_ch_t* pstcTimer2GenCh) 00659 { 00660 if((pstcTimer2GenCh->bPpgCh16 > 1) || 00661 (pstcTimer2GenCh->bPpgCh18 > 1) || 00662 (pstcTimer2GenCh->bPpgCh20 > 1) || 00663 (pstcTimer2GenCh->bPpgCh22 > 1) ) 00664 { 00665 return ErrorInvalidParameter; 00666 } 00667 00668 bFM0P_MFT_PPG_TTCR2_TRG16O = ((pstcTimer2GenCh->bPpgCh16 == 1) ? 1 : 0); 00669 bFM0P_MFT_PPG_TTCR2_TRG18O = ((pstcTimer2GenCh->bPpgCh18 == 1) ? 1 : 0); 00670 bFM0P_MFT_PPG_TTCR2_TRG20O = ((pstcTimer2GenCh->bPpgCh20 == 1) ? 1 : 0); 00671 bFM0P_MFT_PPG_TTCR2_TRG22O = ((pstcTimer2GenCh->bPpgCh22 == 1) ? 1 : 0); 00672 return Ok; 00673 } 00674 00675 #if (PDL_INTERRUPT_ENABLE_PPG == PDL_ON) 00676 00694 en_result_t Ppg_EnableInt(uint8_t u8Ch, en_ppg_int_mode_t enIntMode, func_ptr_t pfnCallback) 00695 { 00696 volatile uint8_t *pu8Ppgc0Addr; 00697 uint8_t u8Offset, u8Gap; 00698 // Only Ch.0,2,4,8,10,12,16,18,20 can produce interrupt request 00699 if((u8Ch != PPG_CH0) && 00700 (u8Ch != PPG_CH2) && 00701 (u8Ch != PPG_CH4) && 00702 (u8Ch != PPG_CH8) && 00703 (u8Ch != PPG_CH10) && 00704 (u8Ch != PPG_CH12) && 00705 (u8Ch != PPG_CH16) && 00706 (u8Ch != PPG_CH18) && 00707 (u8Ch != PPG_CH20) ) 00708 { 00709 return ErrorInvalidParameter; 00710 } 00711 00712 // Check other parameter 00713 if((enIntMode > PpgHighAndLowUnderflow) || 00714 (pfnCallback == NULL)) 00715 { 00716 return ErrorInvalidParameter; 00717 } 00718 00719 u8Offset = u8Ch%4; 00720 u8Gap = u8Ch/4; 00721 pu8Ppgc0Addr = (uint8_t*)FM0P_MFT_PPG_BASE + 0x200 + u8Gap*0x40 + u8Offset*2 + 1; 00722 00723 if((u8Ch == PPG_CH0) || (u8Ch == PPG_CH2) || (u8Ch == PPG_CH4)) 00724 { 00725 pfnPpgCallback[u8Ch/2] = pfnCallback; 00726 } 00727 else if((u8Ch == PPG_CH8) || (u8Ch == PPG_CH10) || (u8Ch == PPG_CH12)) 00728 { 00729 pfnPpgCallback[(u8Ch-2)/2] = pfnCallback; 00730 } 00731 else if((u8Ch == PPG_CH16) || (u8Ch == PPG_CH18) || (u8Ch == PPG_CH20)) 00732 { 00733 pfnPpgCallback[(u8Ch-4)/2] = pfnCallback; 00734 } 00735 *pu8Ppgc0Addr |= (1ul<<7); 00736 00737 Ppg_InitNvic(u8Ch); 00738 00739 return Ok; 00740 } 00741 00754 en_result_t Ppg_DisableInt(uint8_t u8Ch) 00755 { 00756 volatile uint8_t *pu8Ppgc0Addr; 00757 uint8_t u8Offset, u8Gap; 00758 // Only Ch.0,2,4,8,10,12,16,18,20 can produce interrupt request 00759 if((u8Ch != PPG_CH0) && 00760 (u8Ch != PPG_CH2) && 00761 (u8Ch != PPG_CH4) && 00762 (u8Ch != PPG_CH8) && 00763 (u8Ch != PPG_CH10) && 00764 (u8Ch != PPG_CH12) && 00765 (u8Ch != PPG_CH16) && 00766 (u8Ch != PPG_CH18) && 00767 (u8Ch != PPG_CH20) ) 00768 { 00769 return ErrorInvalidParameter; 00770 } 00771 00772 u8Offset = u8Ch%4; 00773 u8Gap = u8Ch/4; 00774 pu8Ppgc0Addr = (uint8_t*)FM0P_MFT_PPG_BASE + 0x200 + u8Gap*0x40 + u8Offset*2 + 1; 00775 00776 if((u8Ch == PPG_CH0) || (u8Ch == PPG_CH2) || (u8Ch == PPG_CH4)) 00777 { 00778 pfnPpgCallback[u8Ch/2] = NULL; 00779 } 00780 else if((u8Ch == PPG_CH8) || (u8Ch == PPG_CH10) || (u8Ch == PPG_CH12)) 00781 { 00782 pfnPpgCallback[(u8Ch-2)/2] = NULL; 00783 } 00784 else if((u8Ch == PPG_CH16) || (u8Ch == PPG_CH18) || (u8Ch == PPG_CH20)) 00785 { 00786 pfnPpgCallback[(u8Ch-4)/2] = NULL; 00787 } 00788 *pu8Ppgc0Addr &= ~(1ul<<7); 00789 00790 Ppg_DeInitNvic(u8Ch); 00791 00792 return Ok; 00793 } 00794 00795 #endif 00796 00808 en_int_flag_t Ppg_GetIntFlag(uint8_t u8Ch) 00809 { 00810 volatile uint8_t *pu8Ppgc0Addr; 00811 uint8_t u8Offset, u8Gap; 00812 en_int_flag_t enFlag; 00813 // Only Ch.0,2,4,8,10,12,16,18,20 can produce interrupt request 00814 if((u8Ch != PPG_CH0) && 00815 (u8Ch != PPG_CH2) && 00816 (u8Ch != PPG_CH4) && 00817 (u8Ch != PPG_CH8) && 00818 (u8Ch != PPG_CH10) && 00819 (u8Ch != PPG_CH12) && 00820 (u8Ch != PPG_CH16) && 00821 (u8Ch != PPG_CH18) && 00822 (u8Ch != PPG_CH20) ) 00823 { 00824 return PdlClr; 00825 } 00826 00827 u8Offset = u8Ch%4; 00828 u8Gap = u8Ch/4; 00829 pu8Ppgc0Addr = (uint8_t*)FM0P_MFT_PPG_BASE + 0x200 + u8Gap*0x40 + u8Offset*2 + 1; 00830 00831 if((*pu8Ppgc0Addr & 0x40) == 0x40) 00832 { 00833 enFlag = PdlSet; 00834 } 00835 else 00836 { 00837 enFlag = PdlClr; 00838 } 00839 00840 return enFlag; 00841 } 00842 00855 en_result_t Ppg_ClrIntFlag(uint8_t u8Ch) 00856 { 00857 volatile uint8_t *pu8Ppgc0Addr, *pu8Ppgc1Addr; 00858 uint8_t u8Offset, u8Gap; 00859 // Only Ch.0,2,4,8,10,12,16,18,20 can produce interrupt request 00860 if((u8Ch != PPG_CH0) && 00861 (u8Ch != PPG_CH2) && 00862 (u8Ch != PPG_CH4) && 00863 (u8Ch != PPG_CH8) && 00864 (u8Ch != PPG_CH10) && 00865 (u8Ch != PPG_CH12) && 00866 (u8Ch != PPG_CH16) && 00867 (u8Ch != PPG_CH18) && 00868 (u8Ch != PPG_CH20) ) 00869 { 00870 return ErrorInvalidParameter; 00871 } 00872 00873 u8Offset = u8Ch%4; 00874 u8Gap = u8Ch/4; 00875 pu8Ppgc0Addr = (uint8_t*)FM0P_MFT_PPG_BASE + 0x200 + u8Gap*0x40 + u8Offset*2 + 1; 00876 pu8Ppgc1Addr = (uint8_t*)FM0P_MFT_PPG_BASE + 0x200 + u8Gap*0x40 + u8Offset*2 ; 00877 00878 // Clear interrupt flag of both even and odd channel 00879 *pu8Ppgc0Addr &= ~(1ul<<6); 00880 *pu8Ppgc1Addr &= ~(1ul<<6); 00881 00882 return Ok; 00883 } 00884 00899 en_result_t Ppg_SetLevelWidth(uint8_t u8Ch, uint8_t u8LowWidth, uint8_t u8HighWidth) 00900 { 00901 volatile uint8_t *pu8Prll0Addr, *pu8Prlh0Addr; 00902 uint8_t u8Offset, u8Gap; 00903 00904 if(u8Ch > PPG_CH23) 00905 { 00906 return ErrorInvalidParameter; 00907 } 00908 00909 u8Offset = u8Ch%4; 00910 u8Gap = u8Ch/4; 00911 pu8Prll0Addr = (uint8_t*)FM0P_MFT_PPG_BASE + 0x208 + u8Gap*0x40 + u8Offset*4; 00912 pu8Prlh0Addr = (uint8_t*)FM0P_MFT_PPG_BASE + 0x208 + u8Gap*0x40 + u8Offset*4 + 1; 00913 *pu8Prll0Addr = u8LowWidth; 00914 *pu8Prlh0Addr = u8HighWidth; 00915 return Ok; 00916 } 00917 00929 en_result_t Ppg_InitIgbt(stc_ppg_igbt_config_t* pstcPpgIgbt) 00930 { 00931 if((pstcPpgIgbt == NULL) || 00932 (pstcPpgIgbt->enMode > IgbtStopProhibitionMode) || 00933 (pstcPpgIgbt->enWidth > IgbtFilter32Pclk) || 00934 (pstcPpgIgbt->enTrigInputLevel > IgbtLevelInvert) || 00935 (pstcPpgIgbt->enIgbt0OutputLevel > IgbtLevelInvert) || 00936 (pstcPpgIgbt->enIgbt1OutputLevel > IgbtLevelInvert) ) 00937 { 00938 return ErrorInvalidParameter; 00939 } 00940 // Prohibition mode setting 00941 FM0P_MFT_PPG->IGBTC &= ~(1ul<<7); 00942 FM0P_MFT_PPG->IGBTC |= (uint8_t)((uint8_t)pstcPpgIgbt->enMode<<7); 00943 // Filter width setting 00944 FM0P_MFT_PPG->IGBTC &= ~(7ul<<4); 00945 FM0P_MFT_PPG->IGBTC |= (uint8_t)((uint8_t)pstcPpgIgbt->enWidth<<4); 00946 // Trigger input level setting 00947 FM0P_MFT_PPG->IGBTC &= ~(1ul<<1); 00948 FM0P_MFT_PPG->IGBTC |= (uint8_t)((uint8_t)pstcPpgIgbt->enTrigInputLevel<<1); 00949 // IGBT output level setting 00950 FM0P_MFT_PPG->IGBTC &= ~(1ul<<2); 00951 FM0P_MFT_PPG->IGBTC |= (uint8_t)((uint8_t)pstcPpgIgbt->enIgbt0OutputLevel<<2); 00952 FM0P_MFT_PPG->IGBTC &= ~(1ul<<3); 00953 FM0P_MFT_PPG->IGBTC |= (uint8_t)((uint8_t)pstcPpgIgbt->enIgbt0OutputLevel<<3); 00954 00955 return Ok; 00956 00957 } 00958 00965 void Ppg_EnableIgbtMode(void) 00966 { 00967 FM0P_MFT_PPG->IGBTC |= 1ul; 00968 } 00969 00974 void Ppg_DisableIgbtMode(void) 00975 { 00976 FM0P_MFT_PPG->IGBTC &= ~1ul; 00977 } 00978 00979 #endif