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PDL for FM0+
Version1.0
Peripheral Driverl Library for FM0+
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00001 /******************************************************************************* 00002 * Copyright (C) 2013 Spansion LLC. All Rights Reserved. 00003 * 00004 * This software is owned and published by: 00005 * Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). 00006 * 00007 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 00008 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. 00009 * 00010 * This software contains source code for use with Spansion 00011 * components. This software is licensed by Spansion to be adapted only 00012 * for use in systems utilizing Spansion components. Spansion shall not be 00013 * responsible for misuse or illegal use of this software for devices not 00014 * supported herein. Spansion is providing this software "AS IS" and will 00015 * not be responsible for issues arising from incorrect user implementation 00016 * of the software. 00017 * 00018 * SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, 00019 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 00020 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 00021 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 00022 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 00023 * WARRANTY OF NONINFRINGEMENT. 00024 * SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 00025 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 00026 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 00027 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 00028 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 00029 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 00030 * SAVINGS OR PROFITS, 00031 * EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 00032 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR 00033 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 00034 * FROM, THE SOFTWARE. 00035 * 00036 * This software may be replicated in part or whole for the licensed use, 00037 * with the restriction that this Disclaimer and Copyright notice must be 00038 * included with each copy of this software, whether used in part or whole, 00039 * at all times. 00040 */ 00041 /******************************************************************************/ 00050 #ifndef __BT_H__ 00051 #define __BT_H__ 00052 00053 /******************************************************************************/ 00054 /* Include files */ 00055 /******************************************************************************/ 00056 #include "mcu.h" 00057 #include "pdl_user.h" 00058 00059 #if (defined(PDL_PERIPHERAL_BT_ACTIVE)) 00060 00282 00283 /****************************************************************************** 00284 * Global definitions 00285 ******************************************************************************/ 00286 #define stc_btn_t FM0P_BT_PWM_TypeDef 00287 00288 #define BT0 (*((volatile stc_btn_t *) FM0P_BT0_PWM_BASE)) 00289 #define BT1 (*((volatile stc_btn_t *) FM0P_BT1_PWM_BASE)) 00290 #define BT2 (*((volatile stc_btn_t *) FM0P_BT2_PWM_BASE)) 00291 #define BT3 (*((volatile stc_btn_t *) FM0P_BT3_PWM_BASE)) 00292 #define BT4 (*((volatile stc_btn_t *) FM0P_BT4_PWM_BASE)) 00293 #define BT5 (*((volatile stc_btn_t *) FM0P_BT5_PWM_BASE)) 00294 #define BT6 (*((volatile stc_btn_t *) FM0P_BT6_PWM_BASE)) 00295 #define BT7 (*((volatile stc_btn_t *) FM0P_BT7_PWM_BASE)) 00296 00297 00298 #define BT_INSTANCE_COUNT ((PDL_PERIPHERAL_ENABLE_BT0 == PDL_ON) ? 1 : 0) + \ 00299 ((PDL_PERIPHERAL_ENABLE_BT1 == PDL_ON) ? 1 : 0) + \ 00300 ((PDL_PERIPHERAL_ENABLE_BT2 == PDL_ON) ? 1 : 0) + \ 00301 ((PDL_PERIPHERAL_ENABLE_BT3 == PDL_ON) ? 1 : 0) + \ 00302 ((PDL_PERIPHERAL_ENABLE_BT4 == PDL_ON) ? 1 : 0) + \ 00303 ((PDL_PERIPHERAL_ENABLE_BT5 == PDL_ON) ? 1 : 0) + \ 00304 ((PDL_PERIPHERAL_ENABLE_BT6 == PDL_ON) ? 1 : 0) + \ 00305 ((PDL_PERIPHERAL_ENABLE_BT7 == PDL_ON) ? 1 : 0) 00306 00307 /****************************************************************************** 00308 * Global type definitions 00309 ******************************************************************************/ 00314 typedef enum en_bt_instance_index 00315 { 00316 #if (PDL_PERIPHERAL_ENABLE_BT0 == PDL_ON) 00317 BtInstanceIndexBt0, 00318 #endif 00319 #if (PDL_PERIPHERAL_ENABLE_BT1 == PDL_ON) 00320 BtInstanceIndexBt1, 00321 #endif 00322 #if (PDL_PERIPHERAL_ENABLE_BT2 == PDL_ON) 00323 BtInstanceIndexBt2, 00324 #endif 00325 #if (PDL_PERIPHERAL_ENABLE_BT3 == PDL_ON) 00326 BtInstanceIndexBt3, 00327 #endif 00328 #if (PDL_PERIPHERAL_ENABLE_BT4 == PDL_ON) 00329 BtInstanceIndexBt4, 00330 #endif 00331 #if (PDL_PERIPHERAL_ENABLE_BT5 == PDL_ON) 00332 BtInstanceIndexBt5, 00333 #endif 00334 #if (PDL_PERIPHERAL_ENABLE_BT6 == PDL_ON) 00335 BtInstanceIndexBt6, 00336 #endif 00337 #if (PDL_PERIPHERAL_ENABLE_BT7 == PDL_ON) 00338 BtInstanceIndexBt7, 00339 #endif 00340 BtInstanceIndexMax 00341 } en_bt_instance_index_t; 00342 00347 typedef enum en_bt_io_mode 00348 { 00349 BtIoMode0 = 0u, 00350 BtIoMode1, 00351 BtIoMode2, 00352 BtIoMode3, 00353 BtIoMode4, 00354 BtIoMode5, 00355 BtIoMode6, 00356 BtIoMode7, 00357 BtIoMode8, 00358 00359 }en_bt_io_mode_t; 00360 00365 typedef enum en_bt_timer_mode 00366 { 00367 BtResetMode = 0, 00368 BtPwmMode, 00369 BtPpgMode, 00370 BtRtMode, 00371 BtPwcMode, 00372 00373 }en_bt_timer_mode_t; 00374 00379 typedef enum en_pwm_clock_pres 00380 { 00381 PwmPresNone = 0u, 00382 PwmPres1Div4, 00383 PwmPres1Div16, 00384 PwmPres1Div128, 00385 PwmPres1Div256, 00386 PwmPres1ExtClkRising, 00387 PwmPres1ExtClkFalling, 00388 PwmPres1ExtClkBoth, 00389 PwmPres1Div512, 00390 PwmPres1Div1024, 00391 PwmPres1Div2048, 00392 00393 }en_pwm_clock_pres_t; 00394 00399 typedef enum en_pwm_restart_enable 00400 { 00401 PwmRestartDisable = 0, 00402 PwmRestartEnable, 00403 00404 }en_pwm_restart_enable_t; 00405 00410 typedef enum en_pwm_output_mask 00411 { 00412 PwmOutputNormal = 0, 00413 PwmOutputMask, 00414 00415 }en_pwm_output_mask_t; 00416 00421 typedef enum en_pwm_ext_trig 00422 { 00423 PwmExtTrigDisable = 0, 00424 PwmExtTrigRising, 00425 PwmExtTrigFalling, 00426 PwmExtTrigBoth, 00427 00428 }en_pwm_ext_trig_t; 00429 00434 typedef enum en_pwm_output_polarity 00435 { 00436 PwmPolarityLow = 0, 00437 PwmPolarityHigh, 00438 00439 }en_pwm_output_polarity_t; 00440 00445 typedef enum en_pwm_mode 00446 { 00447 PwmContinuous = 0, 00448 PwmOneshot, 00449 00450 }en_pwm_mode_t; 00451 00456 typedef struct stc_bt_pwm_config 00457 { 00458 en_pwm_clock_pres_t enPres; 00459 en_pwm_restart_enable_t enRestartEn; 00460 en_pwm_output_mask_t enOutputMask; 00461 en_pwm_ext_trig_t enExtTrig; 00462 en_pwm_output_polarity_t enOutputPolarity; 00463 en_pwm_mode_t enMode; 00464 00465 }stc_bt_pwm_config_t; 00466 00471 typedef enum en_bt_pwm_int 00472 { 00473 PwmTrigInt = 0, 00474 PwmDutyMatchInt, 00475 PwmUnderflowInt, 00476 00477 }en_bt_pwm_int_t; 00478 00483 typedef struct stc_pwm_int_sel 00484 { 00485 boolean_t bPwmTrigInt; 00486 boolean_t bPwmDutyMatchInt; 00487 boolean_t bPwmUnderflowInt; 00488 00489 }stc_pwm_int_sel_t; 00490 00495 typedef struct stc_pwm_int_cb 00496 { 00497 func_ptr_t pfnPwmTrigIntCallback; 00498 func_ptr_t pfnPwmDutyMatchIntCallback; 00499 func_ptr_t pfnPwmUnderflowIntCallback; 00500 00501 }stc_pwm_int_cb_t; 00502 00507 typedef enum en_ppg_clock_pres 00508 { 00509 PpgPresNone = 0, 00510 PpgPres1Div4, 00511 PpgPres1Div16, 00512 PpgPres1Div128, 00513 PpgPres1Div256, 00514 PpgPres1ExtClkRising, 00515 PpgPres1ExtClkFalling, 00516 PpgPres1ExtClkBoth, 00517 PpgPres1Div512, 00518 PpgPres1Div1024, 00519 PpgPres1Div2048, 00520 00521 }en_ppg_clock_pres_t; 00522 00527 typedef enum en_ppg_restart_enable 00528 { 00529 PpgRestartDisable = 0, 00530 PpgRestartEnable, 00531 00532 }en_ppg_restart_enable_t; 00533 00538 typedef enum en_ppg_output_mask 00539 { 00540 PpgOutputNormal = 0, 00541 PpgOutputMask, 00542 00543 }en_ppg_output_mask_t; 00544 00549 typedef enum en_ppg_ext_trig 00550 { 00551 PpgExtTrigDisable = 0, 00552 PpgExtTrigRising, 00553 PpgExtTrigFalling, 00554 PpgExtTrigBoth, 00555 00556 }en_ppg_ext_trig_t; 00557 00562 typedef enum en_ppg_output_polarity 00563 { 00564 PpgPolarityLow = 0, 00565 PpgPolarityHigh, 00566 00567 }en_ppg_output_polarity_t; 00568 00573 typedef enum en_ppg_mode 00574 { 00575 PpgContinuous = 0, 00576 PpgOneshot, 00577 00578 }en_ppg_mode_t; 00579 00584 typedef struct stc_bt_ppg_config 00585 { 00586 en_ppg_clock_pres_t enPres; 00587 en_ppg_restart_enable_t enRestartEn; 00588 en_ppg_output_mask_t enOutputMask; 00589 en_ppg_ext_trig_t enExtTrig; 00590 en_ppg_output_polarity_t enOutputPolarity; 00591 en_ppg_mode_t enMode; 00592 00593 }stc_bt_ppg_config_t; 00594 00599 typedef enum en_bt_ppg_int 00600 { 00601 PpgTrigInt = 0, 00602 PpgUnderflowInt, 00603 00604 }en_bt_ppg_int_t; 00605 00610 typedef struct stc_ppg_int_sel 00611 { 00612 boolean_t bPpgTrigInt; 00613 boolean_t bPpgUnderflowInt; 00614 00615 }stc_ppg_int_sel_t; 00616 00621 typedef struct stc_ppg_int_cb 00622 { 00623 func_ptr_t pfnPpgTrigIntCallback; 00624 func_ptr_t pfnPpgUnderflowIntCallback; 00625 00626 }stc_ppg_int_cb_t; 00627 00632 typedef enum en_rt_clock_pres 00633 { 00634 RtPresNone = 0, 00635 RtPres1Div4, 00636 RtPres1Div16, 00637 RtPres1Div128, 00638 RtPres1Div256, 00639 RtPres1ExtClkRising, 00640 RtPres1ExtClkFalling, 00641 RtPres1ExtClkBoth, 00642 RtPres1Div512, 00643 RtPres1Div1024, 00644 RtPres1Div2048, 00645 00646 }en_rt_clock_pres_t; 00647 00652 typedef enum en_rt_ext_trigger 00653 { 00654 RtExtTiggerDisable = 0, 00655 RtExtTiggerRisingEdge, 00656 RtExtTiggerFallingEdge, 00657 RtExtTiggerBothEdge, 00658 RtExtTiggerLowLevel, 00659 RtExtTiggerHighLevel, 00660 00661 }en_rt_ext_trigger_t; 00662 00667 typedef enum en_rt_output_polarity 00668 { 00669 RtPolarityLow = 0, 00670 RtPolarityHigh, 00671 00672 }en_rt_output_polarity_t; 00673 00678 typedef enum en_rt_mode 00679 { 00680 RtReload = 0, 00681 RtOneshot, 00682 00683 }en_rt_mode_t; 00684 00689 typedef enum en_rt_timer_size 00690 { 00691 RtSize16Bit = 0, 00692 RtSize32Bit, 00693 00694 }en_rt_timer_size_t; 00695 00700 typedef struct stc_bt_rt_config 00701 { 00702 en_rt_clock_pres_t enPres; 00703 en_rt_timer_size_t enSize; 00704 en_rt_ext_trigger_t enExtTrig; 00705 en_rt_output_polarity_t enOutputPolarity; 00706 en_rt_mode_t enMode; 00707 00708 }stc_bt_rt_config_t; 00709 00714 typedef enum en_bt_rt_int 00715 { 00716 RtTrigInt = 0, 00717 RtUnderflowInt, 00718 00719 }en_bt_rt_int_t; 00720 00725 typedef struct stc_rt_int_sel 00726 { 00727 boolean_t bRtTrigInt; 00728 boolean_t bRtUnderflowInt; 00729 00730 }stc_rt_int_sel_t; 00731 00736 typedef struct stc_rt_int_cb 00737 { 00738 func_ptr_t pfnRtTrigIntCallback; 00739 func_ptr_t pfnRtUnderflowIntCallback; 00740 00741 }stc_rt_int_cb_t; 00742 00747 typedef enum en_pwc_clock_pres 00748 { 00749 PwcPresNone = 0, 00750 PwcPres1Div4 = 1, 00751 PwcPres1Div16 = 2, 00752 PwcPres1Div128 = 3, 00753 PwcPres1Div256 = 4, 00754 PwcPres1Div512 = 8, 00755 PwcPres1Div1024 = 9, 00756 PwcPres1Div2048 = 10, 00757 00758 }en_pwc_clock_pres_t; 00759 00764 typedef enum en_pwc_measure_edge 00765 { 00766 PwcMeasureRisingToFalling = 0, 00767 PwcMeasureRisingToRising, 00768 PwcMeasureFallingToFalling, 00769 PwcMeasureEitherToEither, 00770 PwcMeasureFallingToRising, 00771 00772 }en_pwc_measure_edge_t; 00773 00778 typedef enum en_pwc_mode 00779 { 00780 PwcContinuous = 0, 00781 PwcOneshot, 00782 00783 }en_pwc_mode_t; 00784 00789 typedef enum en_pwc_timer_size 00790 { 00791 PwcSize16Bit = 0, 00792 PwcSize32Bit, 00793 00794 }en_pwc_timer_size_t; 00795 00800 typedef struct stc_bt_pwc_config 00801 { 00802 en_pwc_clock_pres_t enPres; 00803 en_pwc_timer_size_t enSize; 00804 en_pwc_measure_edge_t enMeasureEdge; 00805 en_pwc_mode_t enMode; 00806 00807 }stc_bt_pwc_config_t; 00808 00813 typedef enum en_bt_pwc_int 00814 { 00815 PwcMeasureCompleteInt = 0, 00816 PwcMeasureOverflowInt, 00817 00818 }en_bt_pwc_int_t; 00819 00824 typedef struct stc_pwc_int_sel 00825 { 00826 boolean_t bPwcMeasCmpInt; 00827 boolean_t bPwcMeasOverflowInt; 00828 00829 }stc_pwc_int_sel_t; 00830 00835 typedef struct stc_pwc_int_cb 00836 { 00837 func_ptr_t pfnPwcMeasCmpCallback; 00838 func_ptr_t pfnPwcMeasOverflowCallback; 00839 00840 }stc_pwc_int_cb_t; 00841 00846 typedef struct stc_bt_intern_data 00847 { 00848 func_ptr_t pfnBit0IntCallback; 00849 func_ptr_t pfnBit1IntCallback; 00850 func_ptr_t pfnBit2IntCallback; 00851 } stc_bt_intern_data_t ; 00852 00857 typedef struct stc_bt_instance_data 00858 { 00859 volatile stc_btn_t* pstcInstance; 00860 stc_bt_intern_data_t stcInternData; 00861 } stc_bt_instance_data_t; 00862 00863 /******************************************************************************/ 00864 /* Global variable declarations ('extern', definition in C source) */ 00865 /******************************************************************************/ 00867 extern stc_bt_instance_data_t m_astcBtInstanceDataLut[BT_INSTANCE_COUNT]; 00868 00869 /******************************************************************************/ 00870 /* Global function prototypes (definition in C source) */ 00871 /******************************************************************************/ 00872 /* C binding of definitions if building with C++ compiler */ 00873 #ifdef __cplusplus 00874 extern "C" 00875 { 00876 #endif 00877 /* 1. Configure BT IO mode */ 00878 en_result_t Bt_ConfigIOMode(volatile stc_btn_t* pstcBt, en_bt_io_mode_t enIoMode); 00879 00880 /* 2. Select BT timer Mode */ 00881 en_result_t Bt_SelTimerMode(volatile stc_btn_t* pstcBt, en_bt_timer_mode_t enTimerMode); 00882 00883 /* 3. Timer configuration */ 00884 /* 3.1 PWM timer */ 00885 /* Init */ 00886 en_result_t Bt_Pwm_Init(volatile stc_btn_t* pstcBt, stc_bt_pwm_config_t* pstcPwmConfig); 00887 en_result_t Bt_Pwm_DeInit(volatile stc_btn_t* pstcBt); 00888 /* Func/Int Enable/Disable */ 00889 en_result_t Bt_Pwm_EnableCount(volatile stc_btn_t* pstcBt); 00890 en_result_t Bt_Pwm_DisableCount(volatile stc_btn_t* pstcBt); 00891 en_result_t Bt_Pwm_EnableSwTrig(volatile stc_btn_t* pstcBt); 00892 #if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) || \ 00893 (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) || \ 00894 (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) || \ 00895 (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) 00896 en_result_t Bt_Pwm_EnableInt(volatile stc_btn_t* pstcBt, stc_pwm_int_sel_t* pstcIntSel, 00897 stc_pwm_int_cb_t* pstcIntCallback); 00898 en_result_t Bt_Pwm_DisableInt(volatile stc_btn_t* pstcBt, stc_pwm_int_sel_t* pstcIntSel); 00899 #endif 00900 /* Interrupt flag read/clear */ 00901 en_int_flag_t Bt_Pwm_GetIntFlag(volatile stc_btn_t* pstcBt, en_bt_pwm_int_t enIntType); 00902 en_result_t Bt_Pwm_ClrIntFlag(volatile stc_btn_t* pstcBt, en_bt_pwm_int_t enIntType); 00903 /* Write/read count */ 00904 en_result_t Bt_Pwm_WriteCycleVal(volatile stc_btn_t* pstcBt, uint16_t u16Cycle); 00905 en_result_t Bt_Pwm_WriteDutyVal(volatile stc_btn_t* pstcBt, uint16_t u16Duty); 00906 uint16_t Bt_Pwm_ReadCurCnt(volatile stc_btn_t* pstcBt); 00907 00908 /* 3.2 PPG timer */ 00909 /* Init */ 00910 en_result_t Bt_Ppg_Init(volatile stc_btn_t* pstcBt, stc_bt_ppg_config_t* pstcPpgConfig); 00911 en_result_t Bt_Ppg_DeInit(volatile stc_btn_t* pstcBt); 00912 /* Func/Int Enable/Disable */ 00913 en_result_t Bt_Ppg_EnableCount(volatile stc_btn_t* pstcBt); 00914 en_result_t Bt_Ppg_DisableCount(volatile stc_btn_t* pstcBt); 00915 en_result_t Bt_Ppg_EnableSwTrig(volatile stc_btn_t* pstcBt); 00916 #if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) || \ 00917 (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) || \ 00918 (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) || \ 00919 (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) 00920 en_result_t Bt_Ppg_EnableInt(volatile stc_btn_t* pstcBt, stc_ppg_int_sel_t* pstcIntSel, 00921 stc_ppg_int_cb_t* pstcIntCallback); 00922 en_result_t Bt_Ppg_DisableInt(volatile stc_btn_t* pstcBt, stc_ppg_int_sel_t* pstcIntSel); 00923 #endif 00924 /* Interrupt flag read/clear */ 00925 en_int_flag_t Bt_Ppg_GetIntFlag(volatile stc_btn_t* pstcBt, en_bt_ppg_int_t enIntType); 00926 en_result_t Bt_Ppg_ClrIntFlag(volatile stc_btn_t* pstcBt, en_bt_ppg_int_t enIntType); 00927 /* Write/read count */ 00928 en_result_t Bt_Ppg_WriteLowWidthVal(volatile stc_btn_t* pstcBt, uint16_t u16Val); 00929 en_result_t Bt_Ppg_WriteHighWidthVal(volatile stc_btn_t* pstcBt, uint16_t u16Val); 00930 uint16_t Bt_Ppg_ReadCurCnt(volatile stc_btn_t* pstcBt); 00931 00932 /* 3.3 RT timer */ 00933 /* Init */ 00934 en_result_t Bt_Rt_Init(volatile stc_btn_t* pstcBt, stc_bt_rt_config_t* pstcRtConfig); 00935 en_result_t Bt_Rt_DeInit(volatile stc_btn_t* pstcBt); 00936 /* Func/Int Enable/Disable */ 00937 en_result_t Bt_Rt_EnableCount(volatile stc_btn_t* pstcBt); 00938 en_result_t Bt_Rt_DisableCount(volatile stc_btn_t* pstcBt); 00939 en_result_t Bt_Rt_EnableSwTrig(volatile stc_btn_t* pstcBt); 00940 #if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) || \ 00941 (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) || \ 00942 (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) || \ 00943 (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) 00944 en_result_t Bt_Rt_EnableInt(volatile stc_btn_t* pstcBt, stc_rt_int_sel_t* pstcIntSel, 00945 stc_rt_int_cb_t* pstcIntCallback); 00946 en_result_t Bt_Rt_DisableInt(volatile stc_btn_t* pstcBt, stc_rt_int_sel_t* pstcIntSel); 00947 #endif 00948 /* Interrupt flag read/clear */ 00949 en_int_flag_t Bt_Rt_GetIntFlag(volatile stc_btn_t* pstcBt, en_bt_rt_int_t enIntType); 00950 en_result_t Bt_Rt_ClrIntFlag(volatile stc_btn_t* pstcBt, en_bt_rt_int_t enIntType); 00951 /* Write/read count */ 00952 en_result_t Bt_Rt_WriteCycleVal(volatile stc_btn_t* pstcBt, uint16_t u16Val); 00953 uint16_t Bt_Rt_ReadCurCnt(volatile stc_btn_t* pstcBt); 00954 00955 /* 3.4 PWC timer */ 00956 /* Init */ 00957 en_result_t Bt_Pwc_Init(volatile stc_btn_t* pstcBt, stc_bt_pwc_config_t* pstcPwcConfig); 00958 en_result_t Bt_Pwc_DeInit(volatile stc_btn_t* pstcBt); 00959 /* Func/Int Enable/Disable */ 00960 en_result_t Bt_Pwc_EnableCount(volatile stc_btn_t* pstcBt); 00961 en_result_t Bt_Pwc_DisableCount(volatile stc_btn_t* pstcBt); 00962 #if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) || \ 00963 (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) || \ 00964 (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) || \ 00965 (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) 00966 en_result_t Bt_Pwc_EnableInt(volatile stc_btn_t* pstcBt, stc_pwc_int_sel_t* pstcIntSel, 00967 stc_pwc_int_cb_t* pstcIntCallback); 00968 en_result_t Bt_Pwc_DisableInt(volatile stc_btn_t* pstcBt, stc_pwc_int_sel_t* pstcIntSel); 00969 #endif 00970 /* Interrupt flag read/clear */ 00971 en_int_flag_t Bt_Pwc_GetIntFlag(volatile stc_btn_t* pstcBt, en_bt_pwc_int_t enIntType); 00972 en_result_t Bt_Pwc_ClrIntFlag(volatile stc_btn_t* pstcBt, en_bt_pwc_int_t enIntType); 00973 en_stat_flag_t Bt_Pwc_GetErrorFlag(volatile stc_btn_t* pstcBt); 00974 /* Write/read count */ 00975 uint16_t Bt_Pwc_Get16BitMeasureData(volatile stc_btn_t* pstcBt); 00976 uint32_t Bt_Pwc_Get32BitMeasureData(volatile stc_btn_t* pstcBt); 00977 00978 /* 4. IRQ handler */ 00979 void Bt_IrqHandler( volatile stc_btn_t* pstcBt, 00980 stc_bt_intern_data_t* pstcBtInternData) ; 00981 /* 5. Start/stop BT simultaneously */ 00982 void Bt_SetSimultaneousStart(uint16_t u16Value); 00983 00984 #ifdef __cplusplus 00985 } 00986 #endif 00987 00989 00990 #endif // #if (defined(PDL_PERIPHERAL_BT_ACTIVE)) 00991 00992 #endif // #if __BT_H__ 00993 /******************************************************************************/ 00994 /* EOF (not truncated) */ 00995 /******************************************************************************/