PDL for FM0+  Version1.0
Peripheral Driverl Library for FM0+
Clock Functions (CLK)

Data Structures

struct  stc_clk_intern_data
 Datatype for holding internal data needed for CLK. More...
struct  stc_clk_config
 Clock configuration. More...

Defines

#define FM0P_PSW_TMR_PINC_BITPOS   0x10u
#define FM0P_INT_ENR_PCSE_BITPOS   0x04u
#define FM0P_INT_ENR_SCSE_BITPOS   0x02u
#define FM0P_INT_ENR_MCSE_BITPOS   0x01u
#define FM0P_INT_STR_PCSI_BITPOS   0x04u
#define FM0P_INT_STR_SCSI_BITPOS   0x02u
#define FM0P_INT_STR_MCSI_BITPOS   0x01u
#define FM0P_INT_CLR_PCSC_BITPOS   0x04u
#define FM0P_INT_CLR_SCSC_BITPOS   0x02u
#define FM0P_INT_CLR_MCSC_BITPOS   0x01u

Typedefs

typedef enum en_clk_source en_clk_source_t
 Clock Source.
typedef enum en_clk_baseclkdiv en_clk_baseclkdiv_t
 Base Clock Prescaler Settings.
typedef enum en_clk_apb0div en_clk_apb0div_t
 APB0 Prescaler Settings.
typedef enum en_clk_apb1div en_clk_apb1div_t
 APB1 Prescaler Settings.
typedef enum en_clk_scowaittime en_clk_scowaittime_t
 Sub Clock oscillation stabilization wait time.
typedef enum en_clk_mcowaittime en_clk_mcowaittime_t
 Main Clock oscillation stabilization wait time.
typedef enum en_clk_pllowaittime en_clk_pllowaittime_t
 PLL Clock oscillation stabilization wait time.
typedef enum en_clk_pll_src en_clk_pll_src_t
 PLL SourceClock (PINC bit of PSW_TMR)
typedef struct stc_clk_intern_data stc_clk_intern_data_t
 Datatype for holding internal data needed for CLK.
typedef enum en_clk_gate_peripheral en_clk_gate_peripheral_t
 Clock Gate peripheral enumerators.
typedef enum
en_clk_reset_peripheral 
en_clk_reset_peripheral_t
 Reset peripheral enumerators.
typedef struct stc_clk_config stc_clk_config_t
 Clock configuration.

Enumerations

enum  en_clk_source {
  ClkMain = 0, ClkSub = 1, ClkHsCr = 2, ClkLsCr = 3,
  ClkPll = 4, ClkHsCrPll = 5
}
 Clock Source. More...
enum  en_clk_baseclkdiv {
  BaseClkDiv1 = 0, BaseClkDiv2 = 1, BaseClkDiv3 = 2, BaseClkDiv4 = 3,
  BaseClkDiv6 = 4, BaseClkDiv8 = 5, BaseClkDiv16 = 6, BaseClkErr = 7
}
 Base Clock Prescaler Settings. More...
enum  en_clk_apb0div { Apb0Div1 = 0, Apb0Div2 = 1, Apb0Div4 = 2, Apb0Div8 = 3 }
 APB0 Prescaler Settings. More...
enum  en_clk_apb1div { Apb1Div1 = 0, Apb1Div2 = 1, Apb1Div4 = 2, Apb1Div8 = 3 }
 APB1 Prescaler Settings. More...
enum  en_clk_scowaittime {
  ScoWaitExp10 = 0, ScoWaitExp11 = 1, ScoWaitExp12 = 2, ScoWaitExp13 = 3,
  ScoWaitExp14 = 4, ScoWaitExp15 = 5, ScoWaitExp16 = 6, ScoWaitExp17 = 7,
  ScoWaitExp18 = 8, ScoWaitExp19 = 9, ScoWaitExp20 = 10, ScoWaitExp21 = 11,
  ScoWaitErr = 12
}
 Sub Clock oscillation stabilization wait time. More...
enum  en_clk_mcowaittime {
  McoWaitExp11 = 0, McoWaitExp15 = 1, McoWaitExp16 = 2, McoWaitExp17 = 3,
  McoWaitExp18 = 4, McoWaitExp19 = 5, McoWaitExp110 = 6, McoWaitExp111 = 7,
  McoWaitExp112 = 8, McoWaitExp113 = 9, McoWaitExp114 = 10, McoWaitExp115 = 11,
  McoWaitExp117 = 12, McoWaitExp119 = 13, McoWaitExp121 = 14, McoWaitExp123 = 15
}
 Main Clock oscillation stabilization wait time. More...
enum  en_clk_pllowaittime {
  PlloWaitExp19 = 0, PlloWaitExp110 = 1, PlloWaitExp111 = 2, PlloWaitExp112 = 3,
  PlloWaitExp113 = 4, PlloWaitExp114 = 5, PlloWaitExp115 = 6, PlloWaitExp116 = 7
}
 PLL Clock oscillation stabilization wait time. More...
enum  en_clk_pll_src { PllSrcClkMo = 0, PllSrcClkHc = 123 }
 PLL SourceClock (PINC bit of PSW_TMR) More...
enum  en_clk_gate_peripheral {
  ClkGateGpio = 0, ClkGateDma = 2, ClkGateAdc0 = 3, ClkGateAdc1 = 4,
  ClkGateAdc2 = 5, ClkGateAdc3 = 6, ClkGateMfs0 = 7, ClkGateMfs1 = 8,
  ClkGateMfs2 = 9, ClkGateMfs3 = 10, ClkGateMfs4 = 11, ClkGateMfs5 = 12,
  ClkGateMfs6 = 13, ClkGateMfs7 = 14, ClkGateMfs8 = 15, ClkGateMfs9 = 16,
  ClkGateMfs10 = 17, ClkGateMfs11 = 18, ClkGateMfs12 = 19, ClkGateMfs13 = 20,
  ClkGateMfs14 = 21, ClkGateMfs15 = 22, ClkGateQprc0 = 23, ClkGateQprc1 = 24,
  ClkGateQprc2 = 25, ClkGateQprc3 = 26, ClkGateMft0 = 27, ClkGateMft1 = 28,
  ClkGateMft2 = 29, ClkGateMft3 = 30, ClkGateBt0 = 31, ClkGateBt4 = 32,
  ClkGateBt8 = 33, ClkGateBt12 = 34, ClkGateCan0 = 36, ClkGateCan1 = 37
}
 Clock Gate peripheral enumerators. More...
enum  en_clk_reset_peripheral {
  ClkResetDma = 2, ClkResetAdc0 = 3, ClkResetAdc1 = 4, ClkResetAdc2 = 5,
  ClkResetAdc3 = 6, ClkResetMfs0 = 7, ClkResetMfs1 = 8, ClkResetMfs2 = 9,
  ClkResetMfs3 = 10, ClkResetMfs4 = 11, ClkResetMfs5 = 12, ClkResetMfs6 = 13,
  ClkResetMfs7 = 14, ClkResetMfs8 = 15, ClkResetMfs9 = 16, ClkResetMfs10 = 17,
  ClkResetMfs11 = 18, ClkResetMfs12 = 19, ClkResetMfs13 = 20, ClkResetMfs14 = 21,
  ClkResetMfs15 = 22, ClkResetQprc0 = 23, ClkResetQprc1 = 24, ClkResetQprc2 = 25,
  ClkResetQprc3 = 26, ClkResetMft0 = 27, ClkResetMft1 = 28, ClkResetMft2 = 29,
  ClkResetMft3 = 30, ClkResetBt0 = 31, ClkResetBt4 = 32, ClkResetBt8 = 33,
  ClkResetBt12 = 34, ClkResetSdIf = 35, ClkResetCan0 = 36, ClkResetCan1 = 37
}
 Reset peripheral enumerators. More...

Functions

void Clk_IrqHandler (void)
 Clock Stabilization Interrupt Handler.
en_result_t Clk_Init (stc_clk_config_t *pstcClk)
 Initialize system clock according to user configuration.
en_result_t Clk_EnableHscr (boolean_t bBlock)
 Enable high speed CR.
en_result_t Clk_DisableHscr (void)
 Disable Main Clock.
en_result_t Clk_EnableMainClock (boolean_t bBlock)
 Enable Main Clock and wait until it is stable.
en_result_t Clk_DisableMainClock (void)
 Disable Main Clock.
en_result_t Clk_EnableSubClock (boolean_t bBlock)
 Enable Sub Clock.
en_result_t Clk_DisableSubClock (void)
 Disable Sub Clock.
en_result_t Clk_EnablePllClock (boolean_t bBlock)
 Enable PLL Clock.
en_result_t Clk_DisablePllClock (void)
 Disable PLL Clock.
en_result_t Clk_SetSource (en_clk_source_t enSource)
 Set Clock Source.
en_result_t Clk_PeripheralClockEnable (en_clk_gate_peripheral_t enPeripheral)
 Enables the clock gate of a peripheral.
boolean_t Clk_PeripheralGetClockState (en_clk_gate_peripheral_t enPeripheral)
 Read the clock gate state of a peripheral.
en_result_t Clk_PeripheralClockDisable (en_clk_gate_peripheral_t enPeripheral)
 Disables the clock gate of a peripheral.
en_result_t Clk_PeripheralSetReset (en_clk_reset_peripheral_t enPeripheral)
 Set reset bit a peripheral.
en_result_t Clk_PeripheralClearReset (en_clk_reset_peripheral_t enPeripheral)
 Clear reset bit a peripheral.

Variables

stc_clk_intern_data_t stcClkInternData
 Store the internal data of clock.
stc_clk_intern_data_t stcClkInternData
 Store the internal data of clock.

Detailed Description

Provided CLK module functions:

Clk_Init() initializes the system clock according to the configuration of the structure type stc_clk_config_t. This function provides another method to configure system clock beside the CMSIS way.

Clk_EnableHscr() enables the high speed CR and Clk_DisableHscr() disables high speed CR.

Clk_EnableMainClock() enables main clock and Clk_DisableMainClock() disables main clock.

Clk_EnableSubClock() enables sub clock and Clk_DisableSubClock() disables sub clock.

Clk_EnablePllClock() enables PLL clock and Clk_DisablePllClock() disables PLL clock.

Clk_SetSource() set the source clock for system clock according to the the enumeration type en_clk_source_t. Before calling this function, the used clock should be enabled.

Clk_PeripheralClockEnable() enables the clock supply to the peripheral selected and Clk_PeripheralClockDisable() disables the clock supply to the peripheral selected. At default status, the clock is supplied. Clk_PeripheralGetClockState() reads the clock status of the peripheral selected.

Calling Clk_PeripheralSetReset() first and then Clk_PeripheralClearReset() can reset a peripheral.


Define Documentation

#define FM0P_INT_CLR_MCSC_BITPOS   0x01u

Definition at line 141 of file clk.h.

Referenced by Clk_IrqHandler().

#define FM0P_INT_CLR_PCSC_BITPOS   0x04u

Definition at line 139 of file clk.h.

Referenced by Clk_IrqHandler().

#define FM0P_INT_CLR_SCSC_BITPOS   0x02u

Definition at line 140 of file clk.h.

Referenced by Clk_IrqHandler().

#define FM0P_INT_ENR_MCSE_BITPOS   0x01u

Definition at line 131 of file clk.h.

#define FM0P_INT_ENR_PCSE_BITPOS   0x04u

Definition at line 129 of file clk.h.

#define FM0P_INT_ENR_SCSE_BITPOS   0x02u

Definition at line 130 of file clk.h.

#define FM0P_INT_STR_MCSI_BITPOS   0x01u

Definition at line 136 of file clk.h.

Referenced by Clk_IrqHandler().

#define FM0P_INT_STR_PCSI_BITPOS   0x04u

Definition at line 134 of file clk.h.

Referenced by Clk_IrqHandler().

#define FM0P_INT_STR_SCSI_BITPOS   0x02u

Definition at line 135 of file clk.h.

Referenced by Clk_IrqHandler().

#define FM0P_PSW_TMR_PINC_BITPOS   0x10u

Definition at line 126 of file clk.h.


Typedef Documentation

APB0 Prescaler Settings.

Enumeration of the dividers of the APB0 (PCLK0)

APB1 Prescaler Settings.

Enumeration of the dividers of the APB0 (PCLK1)

Base Clock Prescaler Settings.

Enumeration of the dividers of the Base Clock (HCLK)

Clock Gate peripheral enumerators.

Main Clock oscillation stabilization wait time.

Enumeration for the Main Clock oscillation stabilization wait time settings

PLL SourceClock (PINC bit of PSW_TMR)

Enumeration for the PLL Clock Source.

Attention:
HS-RC source is only available if used device supports PLL-CLKHC setting! PINC bit availability is not checked in this driver!

PLL Clock oscillation stabilization wait time.

Enumeration for the PLL Clock oscillation stabilization wait time settings

Reset peripheral enumerators.

Sub Clock oscillation stabilization wait time.

Enumeration for the Sub Clock oscillation stabilization wait time settings

Clock Source.

Differentiator for the different clock sources

Note:
The enumerated values do not correspond to the RCS/RCM bits of the clock control and status registers due to having upward compatibility, if this bit coding may change in future devices. The correct bit patterns are set by switch(en_clk_source)/case statements individually in the Clk_SetSource() function.

Clock configuration.

The Clock configuration settings

Datatype for holding internal data needed for CLK.


Enumeration Type Documentation

APB0 Prescaler Settings.

Enumeration of the dividers of the APB0 (PCLK0)

Enumerator:
Apb0Div1 

PCLK0 Division 1/1.

Apb0Div2 

PCLK0 Division 1/2.

Apb0Div4 

PCLK0 Division 1/4.

Apb0Div8 

PCLK0 Division 1/8.

Definition at line 189 of file clk.h.

APB1 Prescaler Settings.

Enumeration of the dividers of the APB0 (PCLK1)

Enumerator:
Apb1Div1 

PCLK1 Division 1/1.

Apb1Div2 

PCLK1 Division 1/2.

Apb1Div4 

PCLK1 Division 1/4.

Apb1Div8 

PCLK1 Division 1/8.

Definition at line 203 of file clk.h.

Base Clock Prescaler Settings.

Enumeration of the dividers of the Base Clock (HCLK)

Enumerator:
BaseClkDiv1 

HCLK Division 1/1.

BaseClkDiv2 

HCLK Division 1/2.

BaseClkDiv3 

HCLK Division 1/3.

BaseClkDiv4 

HCLK Division 1/4.

BaseClkDiv6 

HCLK Division 1/6.

BaseClkDiv8 

HCLK Division 1/8.

BaseClkDiv16 

HCLK Division 1/16.

BaseClkErr 

HCLK prohibited setting.

Definition at line 171 of file clk.h.

Clock Gate peripheral enumerators.

Enumerator:
ClkGateGpio 

GPIO clock gate.

ClkGateDma 

DMA clock gate.

ClkGateAdc0 

ADC0 clock gate.

ClkGateAdc1 

ADC1 clock gate.

ClkGateAdc2 

ADC2 clock gate.

ClkGateAdc3 

ADC3 clock gate.

ClkGateMfs0 

MFS0 clock gate.

ClkGateMfs1 

MFS1 clock gate.

ClkGateMfs2 

MFS2 clock gate.

ClkGateMfs3 

MFS3 clock gate.

ClkGateMfs4 

MFS4 clock gate.

ClkGateMfs5 

MFS5 clock gate.

ClkGateMfs6 

MFS6 clock gate.

ClkGateMfs7 

MFS7 clock gate.

ClkGateMfs8 

MFS8 clock gate.

ClkGateMfs9 

MFS9 clock gate.

ClkGateMfs10 

MFS10 clock gate.

ClkGateMfs11 

MFS11 clock gate.

ClkGateMfs12 

MFS12 clock gate.

ClkGateMfs13 

MFS13 clock gate.

ClkGateMfs14 

MFS14 clock gate.

ClkGateMfs15 

MFS15 clock gate.

ClkGateQprc0 

QPRC0 clock gate.

ClkGateQprc1 

QPRC1 clock gate.

ClkGateQprc2 

QPRC2 clock gate.

ClkGateQprc3 

QPRC3 clock gate.

ClkGateMft0 

MFT0, PPG0/2/4/6 clock gate.

ClkGateMft1 

MFT1, PPG8/10/12/14 clock gate.

ClkGateMft2 

MFT2, PPG16/18/20/22 clock gate.

ClkGateMft3 

MFT3, PPG24/26/28/30 clock gate.

ClkGateBt0 

BT0/1/2/3 clock gate.

ClkGateBt4 

BT4/5/6/7 clock gate.

ClkGateBt8 

BT8/9/10/11 clock gate.

ClkGateBt12 

BT12/13/14/15 clock gate.

ClkGateCan0 

CAN0 clock gate.

ClkGateCan1 

CAN1 clock gate.

Definition at line 311 of file clk.h.

Main Clock oscillation stabilization wait time.

Enumeration for the Main Clock oscillation stabilization wait time settings

Enumerator:
McoWaitExp11 

2^1 / F(CH) => ~500 ns (F(CH) = 4 MHz)

McoWaitExp15 

2^5 / F(CH) => ~8 us (F(CH) = 4 MHz)

McoWaitExp16 

2^6 / F(CH) => ~16 us (F(CH) = 4 MHz)

McoWaitExp17 

2^7 / F(CH) => ~32 us (F(CH) = 4 MHz)

McoWaitExp18 

2^8 / F(CH) => ~64 us (F(CH) = 4 MHz)

McoWaitExp19 

2^9 / F(CH) => ~128 us (F(CH) = 4 MHz)

McoWaitExp110 

2^10 / F(CH) => ~256 us (F(CH) = 4 MHz)

McoWaitExp111 

2^11 / F(CH) => ~512 us (F(CH) = 4 MHz)

McoWaitExp112 

2^12 / F(CH) => ~1.0 ms (F(CH) = 4 MHz)

McoWaitExp113 

2^13 / F(CH) => ~2.0 ms (F(CH) = 4 MHz)

McoWaitExp114 

2^14 / F(CH) => ~4.0 ms (F(CH) = 4 MHz)

McoWaitExp115 

2^15 / F(CH) => ~8.0 ms (F(CH) = 4 MHz)

McoWaitExp117 

2^17 / F(CH) => ~33.0 ms (F(CH) = 4 MHz)

McoWaitExp119 

2^18 / F(CH) => ~131 ms (F(CH) = 4 MHz)

McoWaitExp121 

2^21 / F(CH) => ~524 ms (F(CH) = 4 MHz)

McoWaitExp123 

2^23 / F(CH) => ~2.0 s (F(CH) = 4 MHz)

Definition at line 240 of file clk.h.

PLL SourceClock (PINC bit of PSW_TMR)

Enumeration for the PLL Clock Source.

Attention:
HS-RC source is only available if used device supports PLL-CLKHC setting! PINC bit availability is not checked in this driver!
Enumerator:
PllSrcClkMo 

Use Main Clock as PLL source (always available, default)

PllSrcClkHc 

Use HS-RC Clock as PLL source (only if available!)

Definition at line 288 of file clk.h.

PLL Clock oscillation stabilization wait time.

Enumeration for the PLL Clock oscillation stabilization wait time settings

Enumerator:
PlloWaitExp19 

2^9 / F(CH) => ~128 us (F(CH) = 4 MHz)

PlloWaitExp110 

2^10 / F(CH) => ~256 us (F(CH) = 4 MHz)

PlloWaitExp111 

2^11 / F(CH) => ~512 us (F(CH) = 4 MHz)

PlloWaitExp112 

2^12 / F(CH) => ~1.02 ms (F(CH) = 4 MHz)

PlloWaitExp113 

2^13 / F(CH) => ~2.05 ms (F(CH) = 4 MHz)

PlloWaitExp114 

2^14 / F(CH) => ~4.10 ms (F(CH) = 4 MHz)

PlloWaitExp115 

2^15 / F(CH) => ~8.20 ms (F(CH) = 4 MHz)

PlloWaitExp116 

2^16 / F(CH) => ~16.4 ms (F(CH) = 4 MHz)

Definition at line 266 of file clk.h.

Reset peripheral enumerators.

Enumerator:
ClkResetDma 

DMA Reset.

ClkResetAdc0 

ADC0 Reset.

ClkResetAdc1 

ADC1 Reset.

ClkResetAdc2 

ADC2 Reset.

ClkResetAdc3 

ADC3 Reset.

ClkResetMfs0 

MFS0 Reset.

ClkResetMfs1 

MFS1 Reset.

ClkResetMfs2 

MFS2 Reset.

ClkResetMfs3 

MFS3 Reset.

ClkResetMfs4 

MFS4 Reset.

ClkResetMfs5 

MFS5 Reset.

ClkResetMfs6 

MFS6 Reset.

ClkResetMfs7 

MFS7 Reset.

ClkResetMfs8 

MFS8 Reset.

ClkResetMfs9 

MFS9 Reset.

ClkResetMfs10 

MFS10 Reset.

ClkResetMfs11 

MFS11 Reset.

ClkResetMfs12 

MFS12 Reset.

ClkResetMfs13 

MFS13 Reset.

ClkResetMfs14 

MFS14 Reset.

ClkResetMfs15 

MFS15 Reset.

ClkResetQprc0 

QPRC0 Reset.

ClkResetQprc1 

QPRC1 Reset.

ClkResetQprc2 

QPRC2 Reset.

ClkResetQprc3 

QPRC3 Reset.

ClkResetMft0 

MFT0, PPG0/2/4/6 Reset.

ClkResetMft1 

MFT1, PPG8/10/12/14 Reset.

ClkResetMft2 

MFT2, PPG16/18/20/22 Reset.

ClkResetMft3 

MFT3, PPG24/26/28/30 Reset.

ClkResetBt0 

BT0/1/2/3 Reset.

ClkResetBt4 

BT4/5/6/7 Reset.

ClkResetBt8 

BT8/9/19/11 Reset.

ClkResetBt12 

BT12/13/14/15 Reset.

ClkResetSdIf 

SD Card I/F Reset.

ClkResetCan0 

CAN0 Reset.

ClkResetCan1 

CAN1 Reset.

Definition at line 355 of file clk.h.

Sub Clock oscillation stabilization wait time.

Enumeration for the Sub Clock oscillation stabilization wait time settings

Enumerator:
ScoWaitExp10 

2^10 / F(CL) => ~10.3 ms

ScoWaitExp11 

2^11 / F(CL) => ~20.5 ms

ScoWaitExp12 

2^12 / F(CL) => ~41 ms

ScoWaitExp13 

2^13 / F(CL) => ~82 ms

ScoWaitExp14 

2^14 / F(CL) => ~164 ms

ScoWaitExp15 

2^15 / F(CL) => ~327 ms

ScoWaitExp16 

2^16 / F(CL) => ~655 ms

ScoWaitExp17 

2^17 / F(CL) => ~1.31 s

ScoWaitExp18 

2^17 / F(CL) => ~2.62 s

ScoWaitExp19 

2^17 / F(CL) => ~5.24 s

ScoWaitExp20 

2^17 / F(CL) => ~10.48 s

ScoWaitExp21 

2^17 / F(CL) => ~20.96 s

ScoWaitErr 

Prohibited Setting.

Definition at line 217 of file clk.h.

Clock Source.

Differentiator for the different clock sources

Note:
The enumerated values do not correspond to the RCS/RCM bits of the clock control and status registers due to having upward compatibility, if this bit coding may change in future devices. The correct bit patterns are set by switch(en_clk_source)/case statements individually in the Clk_SetSource() function.
Enumerator:
ClkMain 

Main Clock Oscillator.

ClkSub 

Sub Clock Oscillator.

ClkHsCr 

High-Speed CR Clock Oscillator.

ClkLsCr 

Low-Speed CR Clock Oscillator.

ClkPll 

PLL Clock.

ClkHsCrPll 

High-Speed CR PLL Clock.

Definition at line 155 of file clk.h.


Function Documentation

Disable Main Clock.

This function easily disables the Main Clock. No configuration is needed.

Return values:
OkMain Clock disabled

Definition at line 315 of file clk.c.

References Ok.

Disable Main Clock.

This function easily disables the Main Clock. No configuration is needed.

Return values:
OkMain Clock disabled

Definition at line 355 of file clk.c.

References Ok.

Disable PLL Clock.

This function easily disables the PLL Clock. No configuration is needed.

Return values:
OkPLL Clock disabled

Definition at line 435 of file clk.c.

References Ok.

Disable Sub Clock.

This function easily disables the Sub Clock. No configuration is needed.

Return values:
OkSub Clock disabled

Definition at line 395 of file clk.c.

References Ok.

Enable high speed CR.

This function easily enables the high speed CR. No configuration is needed.

Parameters:
bBlockWait until CR stability or not
  • FALSE Return immediately after enable high speed CR
  • TRUE Wait until CR stability after enable high speed CR
Return values:
Okhigh speed CR enabled

Definition at line 295 of file clk.c.

References Ok, and TRUE.

Enable Main Clock and wait until it is stable.

This function easily enables the Main Clock. No configuration is needed.

Parameters:
bBlockWait until Main Clock stability or not
  • FALSE Return immediately after enable Main Clock
  • TRUE Wait until Main Clock stability after enable Main Clock
Return values:
OkMain Clock enabled

Definition at line 335 of file clk.c.

References Ok, and TRUE.

Enable PLL Clock.

This function easily enables the PLL Clock. No configuration is needed.

Parameters:
bBlockWait until PLL Clock stability or not
  • FALSE Return immediately after enable PLL Clock
  • TRUE Wait until PLL Clock stability after enable PLL Clock
Return values:
OkPLL Clock enabled

Definition at line 415 of file clk.c.

References Ok, and TRUE.

Enable Sub Clock.

This function easily enables the Sub Clock. No configuration is needed.

Parameters:
bBlockWait until Sub Clock stability or not
  • FALSE Return immediately after enable Sub Clock
  • TRUE Wait until Sub Clock stability after enable Sub Clock
Return values:
OkSub Clock enabled

Definition at line 375 of file clk.c.

References Ok, and TRUE.

Initialize system clock according to user configuration.

This function configues clock division, stability time, PLL setting.

Parameters:
[in]pstcClkPointer to clock configuration structure
Return values:
OkClock initialized normally
ErrorInvalidParameterThe parameter is set to error range
Note:
Set the definition CLOCK_SETUP to "CLOCK_SETTING_NONE" when using this function to initialize system clock.

Definition at line 155 of file clk.c.

References Apb0Div1, Apb0Div2, Apb0Div4, Apb0Div8, Apb1Div1, Apb1Div2, Apb1Div4, Apb1Div8, stc_clk_config::bAPB1Disable, BaseClkDiv1, BaseClkDiv16, BaseClkDiv2, BaseClkDiv3, BaseClkDiv4, BaseClkDiv6, BaseClkDiv8, stc_clk_config::bMcoIrq, stc_clk_config::bPllIrq, stc_clk_config::bScoIrq, stc_clk_config::enAPB0Div, stc_clk_config::enAPB1Div, stc_clk_config::enBaseClkDiv, stc_clk_config::enMCOWaitTime, stc_clk_config::enPLLOWaitTime, stc_clk_config::enSCOWaitTime, ErrorInvalidParameter, Ok, stc_clk_intern_data::pfnMcoStabCb, stc_clk_config::pfnMcoStabCb, stc_clk_intern_data::pfnPllStabCb, stc_clk_config::pfnPllStabCb, stc_clk_intern_data::pfnScoStabCb, stc_clk_config::pfnScoStabCb, TRUE, stc_clk_config::u8PllK, stc_clk_config::u8PllM, and stc_clk_config::u8PllN.

Clear reset bit a peripheral.

This function clears the corresponding bit in the MRSTn register to release a peripheral from reset state.

Parameters:
enPeripheralEnumerator of a peripheral, see en_clk_reset_peripheral_t for details
Return values:
OkPeripheral clock enabled
ErrorInvalidParameterPeripheral enumerator does not exist

Definition at line 1030 of file clk.c.

References ClkResetAdc0, ClkResetAdc1, ClkResetAdc2, ClkResetAdc3, ClkResetBt0, ClkResetBt12, ClkResetBt4, ClkResetBt8, ClkResetCan0, ClkResetCan1, ClkResetDma, ClkResetMfs0, ClkResetMfs1, ClkResetMfs10, ClkResetMfs11, ClkResetMfs12, ClkResetMfs13, ClkResetMfs14, ClkResetMfs15, ClkResetMfs2, ClkResetMfs3, ClkResetMfs4, ClkResetMfs5, ClkResetMfs6, ClkResetMfs7, ClkResetMfs8, ClkResetMfs9, ClkResetMft0, ClkResetMft1, ClkResetMft2, ClkResetMft3, ClkResetQprc0, ClkResetQprc1, ClkResetQprc2, ClkResetQprc3, ErrorInvalidParameter, and Ok.

Disables the clock gate of a peripheral.

This function clears the corresponding bit in the CKENn register to disable the clock of a peripheral.

Parameters:
enPeripheralEnumerator of a peripheral, see en_clk_gate_peripheral_t for details
Return values:
OkPeripheral clock disabled
ErrorInvalidParameterPeripheral enumerator does not exist

Definition at line 769 of file clk.c.

References ClkGateAdc0, ClkGateAdc1, ClkGateAdc2, ClkGateAdc3, ClkGateBt0, ClkGateBt12, ClkGateBt4, ClkGateBt8, ClkGateCan0, ClkGateCan1, ClkGateDma, ClkGateGpio, ClkGateMfs0, ClkGateMfs1, ClkGateMfs10, ClkGateMfs11, ClkGateMfs12, ClkGateMfs13, ClkGateMfs14, ClkGateMfs15, ClkGateMfs2, ClkGateMfs3, ClkGateMfs4, ClkGateMfs5, ClkGateMfs6, ClkGateMfs7, ClkGateMfs8, ClkGateMfs9, ClkGateMft0, ClkGateMft1, ClkGateMft2, ClkGateMft3, ClkGateQprc0, ClkGateQprc1, ClkGateQprc2, ClkGateQprc3, ErrorInvalidParameter, and Ok.

Enables the clock gate of a peripheral.

This function sets the corresponding bit in the CKENn register to enable the clock of a peripheral.

Parameters:
enPeripheralEnumerator of a peripheral, see en_clk_gate_peripheral_t for details
Return values:
OkPeripheral clock enabled
ErrorInvalidParameterPeripheral enumerator does not exist

Definition at line 541 of file clk.c.

References ClkGateAdc0, ClkGateAdc1, ClkGateAdc2, ClkGateAdc3, ClkGateBt0, ClkGateBt12, ClkGateBt4, ClkGateBt8, ClkGateCan0, ClkGateCan1, ClkGateDma, ClkGateGpio, ClkGateMfs0, ClkGateMfs1, ClkGateMfs10, ClkGateMfs11, ClkGateMfs12, ClkGateMfs13, ClkGateMfs14, ClkGateMfs15, ClkGateMfs2, ClkGateMfs3, ClkGateMfs4, ClkGateMfs5, ClkGateMfs6, ClkGateMfs7, ClkGateMfs8, ClkGateMfs9, ClkGateMft0, ClkGateMft1, ClkGateMft2, ClkGateMft3, ClkGateQprc0, ClkGateQprc1, ClkGateQprc2, ClkGateQprc3, ErrorInvalidParameter, and Ok.

Read the clock gate state of a peripheral.

This function reads out the corresponding bit in the CKENn register.

Parameters:
enPeripheralEnumerator of a peripheral, see en_clk_gate_peripheral_t for details
Return values:
TRUEPeripheral clock enabled
FALSEPeripheral clock not enabled, peripheral not existing

Definition at line 673 of file clk.c.

References ClkGateAdc0, ClkGateAdc1, ClkGateAdc2, ClkGateAdc3, ClkGateBt0, ClkGateBt12, ClkGateBt4, ClkGateBt8, ClkGateCan0, ClkGateCan1, ClkGateDma, ClkGateGpio, ClkGateMfs0, ClkGateMfs1, ClkGateMfs10, ClkGateMfs11, ClkGateMfs12, ClkGateMfs13, ClkGateMfs14, ClkGateMfs15, ClkGateMfs2, ClkGateMfs3, ClkGateMfs4, ClkGateMfs5, ClkGateMfs6, ClkGateMfs7, ClkGateMfs8, ClkGateMfs9, ClkGateMft0, ClkGateMft1, ClkGateMft2, ClkGateMft3, ClkGateQprc0, ClkGateQprc1, ClkGateQprc2, ClkGateQprc3, FALSE, and TRUE.

Set reset bit a peripheral.

This function sets the corresponding bit in the MRSTn register to set a peripheral in reset state.

Parameters:
enPeripheralEnumerator of a peripheral, see en_clk_reset_peripheral_t for details
Return values:
OkPeripheral clock enabled
ErrorInvalidParameterPeripheral enumerator does not exist

Definition at line 901 of file clk.c.

References ClkResetAdc0, ClkResetAdc1, ClkResetAdc2, ClkResetAdc3, ClkResetBt0, ClkResetBt12, ClkResetBt4, ClkResetBt8, ClkResetCan0, ClkResetCan1, ClkResetDma, ClkResetMfs0, ClkResetMfs1, ClkResetMfs10, ClkResetMfs11, ClkResetMfs12, ClkResetMfs13, ClkResetMfs14, ClkResetMfs15, ClkResetMfs2, ClkResetMfs3, ClkResetMfs4, ClkResetMfs5, ClkResetMfs6, ClkResetMfs7, ClkResetMfs8, ClkResetMfs9, ClkResetMft0, ClkResetMft1, ClkResetMft2, ClkResetMft3, ClkResetQprc0, ClkResetQprc1, ClkResetQprc2, ClkResetQprc3, ErrorInvalidParameter, and Ok.

Set Clock Source.

This function sets the clock source and performs transition, if wanted.

Parameters:
[in]enSourceSystem source clock
  • ClkMain Set Main Clock as system source clock
  • ClkSub Set Sub Clock as system source clock
  • ClkHsCr Set High-speed CR as system source clock
  • ClkLsCr Set Low-speed CR as system source clock
  • ClkPll Set Main PLL clock as system source clock
  • ClkHsCrPll Set High-speed CR PLL clock as system source clock
Return values:
OkClock source set
ErrorInvalidParameterpstcConfig == NULL or Illegal mode
ErrorInvalidModeClock setting not possible

Definition at line 460 of file clk.c.

References ClkHsCr, ClkHsCrPll, ClkLsCr, ClkMain, ClkPll, ClkSub, ErrorInvalidMode, ErrorInvalidParameter, Ok, and TRUE.


Variable Documentation

Store the internal data of clock.

Definition at line 73 of file clk.c.

Store the internal data of clock.

Definition at line 73 of file clk.c.