PDL for FM0+  Version1.0
Peripheral Driverl Library for FM0+
C:/pdl_v10/library/driver/clk/clk.c
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00001 /*******************************************************************************
00002 * Copyright (C) 2013 Spansion LLC. All Rights Reserved. 
00003 *
00004 * This software is owned and published by: 
00005 * Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
00006 *
00007 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 
00008 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
00009 *
00010 * This software contains source code for use with Spansion 
00011 * components. This software is licensed by Spansion to be adapted only 
00012 * for use in systems utilizing Spansion components. Spansion shall not be 
00013 * responsible for misuse or illegal use of this software for devices not 
00014 * supported herein.  Spansion is providing this software "AS IS" and will 
00015 * not be responsible for issues arising from incorrect user implementation 
00016 * of the software.  
00017 *
00018 * SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
00019 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 
00020 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 
00021 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 
00022 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 
00023 * WARRANTY OF NONINFRINGEMENT.  
00024 * SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 
00025 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 
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00027 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 
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00033 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 
00034 * FROM, THE SOFTWARE.  
00035 *
00036 * This software may be replicated in part or whole for the licensed use, 
00037 * with the restriction that this Disclaimer and Copyright notice must be 
00038 * included with each copy of this software, whether used in part or whole, 
00039 * at all times.  
00040 */
00041 /******************************************************************************/
00052 /******************************************************************************/
00053 /* Include files                                                              */
00054 /******************************************************************************/
00055 #include "clk.h"
00056 
00057 #if (defined(PDL_PERIPHERAL_CLK_ACTIVE))
00058 
00064 
00065 /******************************************************************************/
00066 /* Local pre-processor symbols/macros ('#define')                             */
00067 /******************************************************************************/
00068 
00069 /******************************************************************************/
00070 /* Global variable definitions (declared in header file with 'extern')        */
00071 /******************************************************************************/
00072 #if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON)
00073 stc_clk_intern_data_t stcClkInternData; 
00074 #endif
00075 
00076 /******************************************************************************/
00077 /* Local type definitions ('typedef')                                         */
00078 /******************************************************************************/
00079 
00080 /******************************************************************************/
00081 /* Local function prototypes ('static')                                       */
00082 /******************************************************************************/
00083 
00084 /******************************************************************************/
00085 /* Local variable definitions ('static')                                      */
00086 /******************************************************************************/
00087 
00088 /******************************************************************************/
00089 /* Function implementation - global ('extern') and local ('static')           */
00090 /******************************************************************************/
00091 
00096 #if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON)
00097 void Clk_IrqHandler(void)
00098 {
00099   uint8_t u8IntStrReadOut;
00100   
00101   u8IntStrReadOut = FM0P_CRG->INT_STR;
00102   
00103   // PLL stabilization ready?
00104   if (0u != (u8IntStrReadOut & FM0P_INT_STR_PCSI_BITPOS))
00105   {
00106     FM0P_CRG->INT_CLR |= FM0P_INT_CLR_PCSC_BITPOS;  // Clear Irq
00107     
00108     // PLL ready callback if defined
00109     if (stcClkInternData.pfnPllStabCb != NULL)
00110     {
00111       stcClkInternData.pfnPllStabCb();
00112     }
00113   }
00114 
00115   // Sub Clock stabilization ready?  
00116   if (0u != (u8IntStrReadOut & FM0P_INT_STR_SCSI_BITPOS))
00117   {
00118     FM0P_CRG->INT_CLR |= FM0P_INT_CLR_SCSC_BITPOS;  // Clear Irq
00119     
00120     // Sub Clock ready callback if defined
00121     if (stcClkInternData.pfnScoStabCb != NULL)
00122     {
00123       stcClkInternData.pfnScoStabCb();
00124     }
00125   }
00126 
00127   // Main Clock stabilization ready?  
00128   if (0u != (u8IntStrReadOut & FM0P_INT_STR_MCSI_BITPOS))
00129   {
00130     FM0P_CRG->INT_CLR |= FM0P_INT_CLR_MCSC_BITPOS;  // Clear Irq
00131     
00132     // Main Clock ready callback if defined
00133     if (stcClkInternData.pfnMcoStabCb != NULL)
00134     {
00135       stcClkInternData.pfnMcoStabCb();
00136     }
00137   }
00138 }
00139 #endif
00140 
00155 en_result_t Clk_Init(stc_clk_config_t* pstcClk) 
00156 {
00157     if(pstcClk == NULL)
00158     {
00159         return ErrorInvalidParameter;
00160     }
00161     
00162     /* Set base clock divider */
00163     switch(pstcClk->enBaseClkDiv)
00164     {
00165         case BaseClkDiv1:
00166             FM0P_CRG->BSC_PSR_f.BSR = 0u;
00167             break;
00168         case BaseClkDiv2:
00169             FM0P_CRG->BSC_PSR_f.BSR = 1u;
00170             break;    
00171         case BaseClkDiv3:
00172             FM0P_CRG->BSC_PSR_f.BSR = 2u;
00173             break;
00174         case BaseClkDiv4:
00175             FM0P_CRG->BSC_PSR_f.BSR = 3u;
00176             break;
00177         case BaseClkDiv6:
00178             FM0P_CRG->BSC_PSR_f.BSR = 4u;
00179             break;
00180         case BaseClkDiv8:
00181             FM0P_CRG->BSC_PSR_f.BSR = 5u;
00182             break;
00183         case BaseClkDiv16:
00184             FM0P_CRG->BSC_PSR_f.BSR = 6u;
00185             break;    
00186         default:
00187             return ErrorInvalidParameter;
00188             
00189     }
00190     
00191     /* Set APB0 bus clock dividor */
00192     switch(pstcClk->enAPB0Div)
00193     {
00194         case Apb0Div1:
00195             FM0P_CRG->APBC0_PSR_f.APBC0 = 0u;
00196             break;
00197         case Apb0Div2:
00198             FM0P_CRG->APBC0_PSR_f.APBC0 = 1u;
00199             break;
00200         case Apb0Div4:
00201             FM0P_CRG->APBC0_PSR_f.APBC0 = 2u;
00202             break;
00203         case Apb0Div8:
00204             FM0P_CRG->APBC0_PSR_f.APBC0 = 3u;
00205             break;    
00206         default:
00207             return ErrorInvalidParameter;
00208     }
00209     
00210     /* Set APB1 bus clock divider */
00211     switch(pstcClk->enAPB1Div)
00212     {
00213         case Apb1Div1:
00214             FM0P_CRG->APBC1_PSR_f.APBC1 = 0u;
00215             break;
00216         case Apb1Div2:
00217             FM0P_CRG->APBC1_PSR_f.APBC1 = 1u;
00218             break;
00219         case Apb1Div4:
00220             FM0P_CRG->APBC1_PSR_f.APBC1 = 2u;
00221             break;
00222         case Apb1Div8:
00223             FM0P_CRG->APBC1_PSR_f.APBC1 = 3u;
00224             break;    
00225         default:
00226             return ErrorInvalidParameter;
00227     }
00228     
00229     if(pstcClk->bAPB1Disable == TRUE)
00230     {
00231         FM0P_CRG->APBC1_PSR_f.APBC1EN = 0;
00232     }
00233     
00234     /* Configure stability wait time */
00235     FM0P_CRG->CSW_TMR_f.MOWT = pstcClk->enMCOWaitTime;
00236     FM0P_CRG->CSW_TMR_f.SOWT = pstcClk->enSCOWaitTime;
00237     FM0P_CRG->PSW_TMR_f.POWT = pstcClk->enPLLOWaitTime;
00238     
00239 #if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON)    
00240     /* Configure interrupt */
00241     if(pstcClk->bMcoIrq == TRUE)
00242     {
00243         if(pstcClk->pfnMcoStabCb == NULL)
00244         {
00245             return ErrorInvalidParameter;
00246         }
00247         
00248         FM0P_CRG->INT_ENR_f.MCSE = 1;
00249         stcClkInternData.pfnMcoStabCb = pstcClk->pfnMcoStabCb;
00250     }
00251     
00252     if(pstcClk->bScoIrq == TRUE)
00253     {
00254         if(pstcClk->pfnScoStabCb == NULL)
00255         {
00256             return ErrorInvalidParameter;
00257         }
00258         
00259         FM0P_CRG->INT_ENR_f.SCSE = 1;
00260         stcClkInternData.pfnScoStabCb = pstcClk->pfnScoStabCb;
00261     }
00262     
00263     if(pstcClk->bPllIrq == TRUE)
00264     {
00265         if(pstcClk->pfnPllStabCb == NULL)
00266         {
00267             return ErrorInvalidParameter;
00268         }
00269         
00270         FM0P_CRG->INT_ENR_f.PCSE = 1;
00271         stcClkInternData.pfnPllStabCb = pstcClk->pfnPllStabCb;
00272     }
00273 #endif    
00274     
00275     /* Set PLL K, M, N */
00276     FM0P_CRG->PLL_CTL1_f.PLLK = pstcClk->u8PllK - 1;
00277     FM0P_CRG->PLL_CTL1_f.PLLM = pstcClk->u8PllM - 1;
00278     FM0P_CRG->PLL_CTL2_f.PLLN = pstcClk->u8PllN - 1;
00279     
00280     return Ok;
00281 }
00282 
00295 en_result_t Clk_EnableHscr(boolean_t bBlock)
00296 {
00297   FM0P_CRG->SCM_CTL_f.HCRE = 1u;
00298   
00299   if(bBlock == TRUE)
00300   {
00301     while(FM0P_CRG->SCM_STR_f.HCRDY != 1);
00302   }
00303 
00304   return Ok;
00305 } // Clk_EnableMainClock
00306 
00315 en_result_t Clk_DisableHscr(void)
00316 {
00317   FM0P_CRG->SCM_CTL_f.MOSCE = 0u;
00318 
00319   return Ok;
00320 } // Clk_DisableMainClock
00321 
00322 
00335 en_result_t Clk_EnableMainClock(boolean_t bBlock)
00336 {
00337   FM0P_CRG->SCM_CTL_f.MOSCE = 1u;
00338   
00339   if(bBlock == TRUE)
00340   {
00341     while(FM0P_CRG->SCM_STR_f.MORDY != 1);
00342   }
00343 
00344   return Ok;
00345 } // Clk_EnableMainClock
00346 
00355 en_result_t Clk_DisableMainClock(void)
00356 {
00357   FM0P_CRG->SCM_CTL_f.MOSCE = 0u;
00358 
00359   return Ok;
00360 } // Clk_DisableMainClock
00361 
00362 
00375 en_result_t Clk_EnableSubClock(boolean_t bBlock)
00376 {
00377   FM0P_CRG->SCM_CTL_f.SOSCE = 1u;
00378   
00379   if(bBlock == TRUE)
00380   {
00381     while(FM0P_CRG->SCM_STR_f.SORDY != 1);
00382   }
00383 
00384   return Ok;
00385 } // Clk_EnableSubClock
00386 
00395 en_result_t Clk_DisableSubClock(void)
00396 {
00397   FM0P_CRG->SCM_CTL_f.SOSCE = 0u;
00398 
00399   return Ok;
00400 } // Clk_DisableSubClock
00401 
00402 
00415 en_result_t Clk_EnablePllClock(boolean_t bBlock)
00416 {
00417   FM0P_CRG->SCM_CTL_f.PLLE = 1u;
00418   
00419   if(bBlock == TRUE)
00420   {
00421     while(FM0P_CRG->SCM_STR_f.PLRDY != 1);
00422   }
00423 
00424   return Ok;
00425 } // Clk_EnableSubClock
00426 
00435 en_result_t Clk_DisablePllClock(void)
00436 {
00437   FM0P_CRG->SCM_CTL_f.PLLE = 0u;
00438 
00439   return Ok;
00440 } // Clk_DisableSubClock
00441 
00460 en_result_t Clk_SetSource(en_clk_source_t enSource)
00461 {  
00462   uint8_t u8Rcs, u8Rcm;
00463   switch(enSource)
00464   {
00465     case ClkMain:
00466       if ((FM0P_CRG->SCM_CTL_f.MOSCE != TRUE) ||  // Main Oscillator ready?
00467           (FM0P_CRG->SCM_STR_f.MORDY != TRUE))
00468       {
00469         return ErrorInvalidMode ;
00470       }
00471       FM0P_CRG->SCM_CTL_f.RCS = 0x1u;
00472       break;
00473     case ClkSub:
00474       if ((FM0P_CRG->SCM_CTL_f.SOSCE != TRUE) ||  // Sub Oscillator ready?
00475           (FM0P_CRG->SCM_STR_f.SORDY != TRUE))
00476       {
00477         return ErrorInvalidMode ;
00478       }
00479       FM0P_CRG->SCM_CTL_f.RCS = 0x5u;
00480       break;
00481     case ClkHsCr:                                // Always possible
00482       if(FM0P_CRG->SCM_STR_f.HCRDY != TRUE)
00483       {
00484         return ErrorInvalidMode ;
00485       }
00486       FM0P_CRG->SCM_CTL_f.RCS = 0x0u;
00487       break;
00488     case ClkLsCr:                                // Always possible
00489       FM0P_CRG->SCM_CTL_f.RCS = 0x4u;
00490       break;
00491     case ClkHsCrPll:  
00492       if(FM0P_CRG->SCM_STR_f.HCRDY != TRUE)
00493       {
00494         return ErrorInvalidMode ;
00495       }
00496       FM0P_CRG->PSW_TMR_f.PINC = 1;
00497       FM0P_CRG->SCM_CTL_f.RCS = 0x2u;
00498       break;
00499     case ClkPll:                           
00500       if ((FM0P_CRG->SCM_STR_f.MORDY != TRUE) ||  // PLL ready?
00501           (FM0P_CRG->SCM_STR_f.PLRDY != TRUE))
00502       {
00503         return ErrorInvalidMode ;
00504       }
00505       
00506       FM0P_CRG->PSW_TMR_f.PINC = 0;
00507       FM0P_CRG->SCM_CTL_f.RCS = 0x2u;
00508       break;
00509     default:
00510       return ErrorInvalidParameter ;
00511   }
00512 
00513   /* Wait until switch stable */
00514   while(1)
00515   {
00516     u8Rcs = FM0P_CRG->SCM_CTL_f.RCS;
00517     u8Rcm = FM0P_CRG->SCM_STR_f.RCM;
00518     if(u8Rcs == u8Rcm)
00519     {
00520         break;
00521     }
00522   }
00523 
00524   return Ok;
00525 } // Clk_SetSource
00526 
00527 
00541 en_result_t Clk_PeripheralClockEnable(en_clk_gate_peripheral_t enPeripheral)
00542 {
00543   switch (enPeripheral)
00544   {
00545     case ClkGateGpio:
00546       FM0P_PCG->CKEN0_f.GIOCK = 1u;
00547       break;
00548     case ClkGateDma:
00549       FM0P_PCG->CKEN0_f.DMACK = 1u;
00550       break;
00551     case ClkGateAdc0:
00552       FM0P_PCG->CKEN0_f.ADCCK0 = 1u;
00553       break;
00554     case ClkGateAdc1:
00555       FM0P_PCG->CKEN0_f.ADCCK1 = 1u;
00556       break;
00557     case ClkGateAdc2:
00558       FM0P_PCG->CKEN0_f.ADCCK2 = 1u;
00559       break;
00560     case ClkGateAdc3:
00561       FM0P_PCG->CKEN0_f.ADCCK3 = 1u;
00562       break;
00563     case ClkGateMfs0:
00564       FM0P_PCG->CKEN0_f.MFSCK0 = 1u;
00565       break;
00566     case ClkGateMfs1:
00567       FM0P_PCG->CKEN0_f.MFSCK1 = 1u;
00568       break;
00569     case ClkGateMfs2:
00570       FM0P_PCG->CKEN0_f.MFSCK2 = 1u;
00571       break;
00572     case ClkGateMfs3:
00573       FM0P_PCG->CKEN0_f.MFSCK3 = 1u;
00574       break;
00575     case ClkGateMfs4:
00576       FM0P_PCG->CKEN0_f.MFSCK4 = 1u;
00577       break;
00578     case ClkGateMfs5:
00579       FM0P_PCG->CKEN0_f.MFSCK5 = 1u;
00580       break;
00581     case ClkGateMfs6:
00582       FM0P_PCG->CKEN0_f.MFSCK6 = 1u;
00583       break;
00584     case ClkGateMfs7:
00585       FM0P_PCG->CKEN0_f.MFSCK7 = 1u;
00586       break;
00587     case ClkGateMfs8:
00588       FM0P_PCG->CKEN0_f.MFSCK8 = 1u;
00589       break;
00590     case ClkGateMfs9:
00591       FM0P_PCG->CKEN0_f.MFSCK9 = 1u;
00592       break;
00593     case ClkGateMfs10:
00594       FM0P_PCG->CKEN0_f.MFSCK10 = 1u;
00595       break;
00596     case ClkGateMfs11:
00597       FM0P_PCG->CKEN0_f.MFSCK11 = 1u;
00598       break;
00599     case ClkGateMfs12:
00600       FM0P_PCG->CKEN0_f.MFSCK12 = 1u;
00601       break;
00602     case ClkGateMfs13:
00603       FM0P_PCG->CKEN0_f.MFSCK13 = 1u;
00604       break;
00605     case ClkGateMfs14:
00606       FM0P_PCG->CKEN0_f.MFSCK14 = 1u;
00607       break;
00608     case ClkGateMfs15:
00609       FM0P_PCG->CKEN0_f.MFSCK15 = 1u;
00610       break;
00611     case ClkGateQprc0:
00612       FM0P_PCG->CKEN1_f.QDUCK0 = 1u;
00613       break;
00614     case ClkGateQprc1:
00615       FM0P_PCG->CKEN1_f.QDUCK1 = 1u;
00616       break;
00617     case ClkGateQprc2:
00618       FM0P_PCG->CKEN1_f.QDUCK2 = 1u;
00619       break;
00620     case ClkGateQprc3:
00621       FM0P_PCG->CKEN1_f.QDUCK3 = 1u;
00622       break;
00623     case ClkGateMft0:
00624       FM0P_PCG->CKEN1_f.MFTCK0 = 1u;
00625       break;
00626     case ClkGateMft1:
00627       FM0P_PCG->CKEN1_f.MFTCK1 = 1u;
00628       break;
00629     case ClkGateMft2:
00630       FM0P_PCG->CKEN1_f.MFTCK2 = 1u;
00631       break;
00632     case ClkGateMft3:
00633       FM0P_PCG->CKEN1_f.MFTCK3 = 1u;
00634       break;
00635     case ClkGateBt0:
00636       FM0P_PCG->CKEN1_f.BTMCK0 = 1u;
00637       break;
00638     case ClkGateBt4:
00639       FM0P_PCG->CKEN1_f.BTMCK1 = 1u;
00640       break;
00641     case ClkGateBt8:
00642       FM0P_PCG->CKEN1_f.BTMCK2 = 1u;
00643       break;
00644     case ClkGateBt12:
00645       FM0P_PCG->CKEN1_f.BTMCK3 = 1u;
00646       break;
00647     case ClkGateCan0:
00648       FM0P_PCG->CKEN2_f.CANCK0 = 1u;
00649       break;
00650     case ClkGateCan1:
00651       FM0P_PCG->CKEN2_f.CANCK1 = 1u;
00652       break;
00653     default:
00654       return ErrorInvalidParameter;
00655   }
00656   
00657   return Ok;
00658 } // Clk_PeripheralClockEnable
00659 
00673 boolean_t Clk_PeripheralGetClockState(en_clk_gate_peripheral_t enPeripheral)
00674 {
00675   switch (enPeripheral)
00676   {
00677     case ClkGateGpio:
00678       return ((1u == FM0P_PCG->CKEN0_f.GIOCK) ? TRUE : FALSE);
00679     case ClkGateDma:
00680       return ((1u == FM0P_PCG->CKEN0_f.DMACK) ? TRUE : FALSE);
00681     case ClkGateAdc0:
00682       return ((1u == FM0P_PCG->CKEN0_f.ADCCK0) ? TRUE : FALSE);
00683     case ClkGateAdc1:
00684       return ((1u == FM0P_PCG->CKEN0_f.ADCCK1) ? TRUE : FALSE);
00685     case ClkGateAdc2:
00686       return ((1u == FM0P_PCG->CKEN0_f.ADCCK2) ? TRUE : FALSE);
00687     case ClkGateAdc3:
00688       return ((1u == FM0P_PCG->CKEN0_f.ADCCK3) ? TRUE : FALSE);
00689     case ClkGateMfs0:
00690       return ((1u == FM0P_PCG->CKEN0_f.MFSCK0) ? TRUE : FALSE);
00691     case ClkGateMfs1:
00692       return ((1u == FM0P_PCG->CKEN0_f.MFSCK1) ? TRUE : FALSE);
00693     case ClkGateMfs2:
00694       return ((1u == FM0P_PCG->CKEN0_f.MFSCK2) ? TRUE : FALSE);
00695     case ClkGateMfs3:
00696       return ((1u == FM0P_PCG->CKEN0_f.MFSCK3) ? TRUE : FALSE);
00697     case ClkGateMfs4:
00698       return ((1u == FM0P_PCG->CKEN0_f.MFSCK4) ? TRUE : FALSE);
00699     case ClkGateMfs5:
00700       return ((1u == FM0P_PCG->CKEN0_f.MFSCK5) ? TRUE : FALSE);
00701     case ClkGateMfs6:
00702       return ((1u == FM0P_PCG->CKEN0_f.MFSCK6) ? TRUE : FALSE);
00703     case ClkGateMfs7:
00704       return ((1u == FM0P_PCG->CKEN0_f.MFSCK7) ? TRUE : FALSE);
00705     case ClkGateMfs8:
00706       return ((1u == FM0P_PCG->CKEN0_f.MFSCK8) ? TRUE : FALSE);
00707     case ClkGateMfs9:
00708       return ((1u == FM0P_PCG->CKEN0_f.MFSCK9) ? TRUE : FALSE);
00709     case ClkGateMfs10:
00710       return ((1u ==  FM0P_PCG->CKEN0_f.MFSCK10) ? TRUE : FALSE);
00711     case ClkGateMfs11:
00712       return ((1u == FM0P_PCG->CKEN0_f.MFSCK11) ? TRUE : FALSE);
00713     case ClkGateMfs12:
00714       return ((1u == FM0P_PCG->CKEN0_f.MFSCK12) ? TRUE : FALSE);
00715     case ClkGateMfs13:
00716       return ((1u == FM0P_PCG->CKEN0_f.MFSCK13) ? TRUE : FALSE);
00717     case ClkGateMfs14:
00718       return ((1u == FM0P_PCG->CKEN0_f.MFSCK14) ? TRUE : FALSE);
00719     case ClkGateMfs15:
00720       return ((1u == FM0P_PCG->CKEN0_f.MFSCK15) ? TRUE : FALSE);
00721     case ClkGateQprc0:
00722       return ((1u == FM0P_PCG->CKEN1_f.QDUCK0) ? TRUE : FALSE);
00723     case ClkGateQprc1:
00724       return ((1u == FM0P_PCG->CKEN1_f.QDUCK1) ? TRUE : FALSE);
00725     case ClkGateQprc2:
00726       return ((1u == FM0P_PCG->CKEN1_f.QDUCK2) ? TRUE : FALSE);
00727     case ClkGateQprc3:
00728       return ((1u == FM0P_PCG->CKEN1_f.QDUCK3) ? TRUE : FALSE);
00729     case ClkGateMft0:
00730       return ((1u == FM0P_PCG->CKEN1_f.MFTCK0) ? TRUE : FALSE);
00731     case ClkGateMft1:
00732       return ((1u == FM0P_PCG->CKEN1_f.MFTCK1) ? TRUE : FALSE);
00733     case ClkGateMft2:
00734       return ((1u == FM0P_PCG->CKEN1_f.MFTCK2) ? TRUE : FALSE);
00735     case ClkGateMft3:
00736       return ((1u == FM0P_PCG->CKEN1_f.MFTCK3) ? TRUE : FALSE);
00737     case ClkGateBt0:
00738       return ((1u == FM0P_PCG->CKEN1_f.BTMCK0) ? TRUE : FALSE);
00739     case ClkGateBt4:
00740       return ((1u == FM0P_PCG->CKEN1_f.BTMCK1) ? TRUE : FALSE);
00741     case ClkGateBt8:
00742       return ((1u == FM0P_PCG->CKEN1_f.BTMCK2) ? TRUE : FALSE);
00743     case ClkGateBt12:
00744       return ((1u == FM0P_PCG->CKEN1_f.BTMCK3) ? TRUE : FALSE);
00745     case ClkGateCan0:
00746       return ((1u == FM0P_PCG->CKEN2_f.CANCK0) ? TRUE : FALSE);
00747     case ClkGateCan1:
00748       return ((1u == FM0P_PCG->CKEN2_f.CANCK1) ? TRUE : FALSE);
00749     default:
00750       break;
00751   }
00752   
00753   return FALSE; // Peripheral not found -> always FALSE
00754 } // Clk_PeripheralGetClockState
00755 
00769 en_result_t Clk_PeripheralClockDisable(en_clk_gate_peripheral_t enPeripheral)
00770 {
00771   switch (enPeripheral)
00772   {
00773     case ClkGateGpio:
00774       FM0P_PCG->CKEN0_f.GIOCK = 0u;
00775       break;
00776     case ClkGateDma:
00777       FM0P_PCG->CKEN0_f.DMACK = 0u;
00778       break;
00779     case ClkGateAdc0:
00780       FM0P_PCG->CKEN0_f.ADCCK0 = 0u;
00781       break;
00782     case ClkGateAdc1:
00783       FM0P_PCG->CKEN0_f.ADCCK1 = 0u;
00784       break;
00785     case ClkGateAdc2:
00786       FM0P_PCG->CKEN0_f.ADCCK2 = 0u;
00787       break;
00788     case ClkGateAdc3:
00789       FM0P_PCG->CKEN0_f.ADCCK3 = 0u;
00790       break;
00791     case ClkGateMfs0:
00792       FM0P_PCG->CKEN0_f.MFSCK0 = 0u;
00793       break;
00794     case ClkGateMfs1:
00795       FM0P_PCG->CKEN0_f.MFSCK1 = 0u;
00796       break;
00797     case ClkGateMfs2:
00798       FM0P_PCG->CKEN0_f.MFSCK2 = 0u;
00799       break;
00800     case ClkGateMfs3:
00801       FM0P_PCG->CKEN0_f.MFSCK3 = 0u;
00802       break;
00803     case ClkGateMfs4:
00804       FM0P_PCG->CKEN0_f.MFSCK4 = 0u;
00805       break;
00806     case ClkGateMfs5:
00807       FM0P_PCG->CKEN0_f.MFSCK5 = 0u;
00808       break;
00809     case ClkGateMfs6:
00810       FM0P_PCG->CKEN0_f.MFSCK6 = 0u;
00811       break;
00812     case ClkGateMfs7:
00813       FM0P_PCG->CKEN0_f.MFSCK7 = 0u;
00814       break;
00815     case ClkGateMfs8:
00816       FM0P_PCG->CKEN0_f.MFSCK8 = 0u;
00817       break;
00818     case ClkGateMfs9:
00819       FM0P_PCG->CKEN0_f.MFSCK9 = 0u;
00820       break;
00821     case ClkGateMfs10:
00822       FM0P_PCG->CKEN0_f.MFSCK10 = 0u;
00823       break;
00824     case ClkGateMfs11:
00825       FM0P_PCG->CKEN0_f.MFSCK11 = 0u;
00826       break;
00827     case ClkGateMfs12:
00828       FM0P_PCG->CKEN0_f.MFSCK12 = 0u;
00829       break;
00830     case ClkGateMfs13:
00831       FM0P_PCG->CKEN0_f.MFSCK13 = 0u;
00832       break;
00833     case ClkGateMfs14:
00834       FM0P_PCG->CKEN0_f.MFSCK14 = 0u;
00835       break;
00836     case ClkGateMfs15:
00837       FM0P_PCG->CKEN0_f.MFSCK15 = 0u;
00838       break;
00839     case ClkGateQprc0:
00840       FM0P_PCG->CKEN1_f.QDUCK0 = 0u;
00841       break;
00842     case ClkGateQprc1:
00843       FM0P_PCG->CKEN1_f.QDUCK1 = 0u;
00844       break;
00845     case ClkGateQprc2:
00846       FM0P_PCG->CKEN1_f.QDUCK2 = 0u;
00847       break;
00848     case ClkGateQprc3:
00849       FM0P_PCG->CKEN1_f.QDUCK3 = 0u;
00850       break;
00851     case ClkGateMft0:
00852       FM0P_PCG->CKEN1_f.MFTCK0 = 0u;
00853       break;
00854     case ClkGateMft1:
00855       FM0P_PCG->CKEN1_f.MFTCK1 = 0u;
00856       break;
00857     case ClkGateMft2:
00858       FM0P_PCG->CKEN1_f.MFTCK2 = 0u;
00859       break;
00860     case ClkGateMft3:
00861       FM0P_PCG->CKEN1_f.MFTCK3 = 0u;
00862       break;
00863     case ClkGateBt0:
00864       FM0P_PCG->CKEN1_f.BTMCK0 = 0u;
00865       break;
00866     case ClkGateBt4:
00867       FM0P_PCG->CKEN1_f.BTMCK1 = 0u;
00868       break;
00869     case ClkGateBt8:
00870       FM0P_PCG->CKEN1_f.BTMCK2 = 0u;
00871       break;
00872     case ClkGateBt12:
00873       FM0P_PCG->CKEN1_f.BTMCK3 = 0u;
00874       break;
00875     case ClkGateCan0:
00876       FM0P_PCG->CKEN2_f.CANCK0 = 0u;
00877       break;
00878     case ClkGateCan1:
00879       FM0P_PCG->CKEN2_f.CANCK1 = 0u;
00880       break;
00881     default:
00882       return ErrorInvalidParameter;
00883   }
00884   
00885   return Ok;
00886 } // Clk_PeripheralClockDisable
00887 
00901 en_result_t Clk_PeripheralSetReset(en_clk_reset_peripheral_t enPeripheral)
00902 {
00903   switch (enPeripheral)
00904   {
00905     case ClkResetDma:
00906       FM0P_PCG->MRST0_f.DMARST = 1u;
00907       break;
00908     case ClkResetAdc0:
00909       FM0P_PCG->MRST0_f.ADCRST0 = 1u;
00910       break;
00911     case ClkResetAdc1:
00912       FM0P_PCG->MRST0_f.ADCRST1 = 1u;
00913       break;
00914     case ClkResetAdc2:
00915       FM0P_PCG->MRST0_f.ADCRST2 = 1u;
00916       break;
00917     case ClkResetAdc3:
00918       FM0P_PCG->MRST0_f.ADCRST3 = 1u;
00919       break;
00920     case ClkResetMfs0:
00921       FM0P_PCG->MRST0_f.MFSRST0 = 1u;
00922       break;
00923     case ClkResetMfs1:
00924       FM0P_PCG->MRST0_f.MFSRST1 = 1u;
00925       break;
00926     case ClkResetMfs2:
00927       FM0P_PCG->MRST0_f.MFSRST2 = 1u;
00928       break;
00929     case ClkResetMfs3:
00930       FM0P_PCG->MRST0_f.MFSRST3 = 1u;
00931       break;
00932     case ClkResetMfs4:
00933       FM0P_PCG->MRST0_f.MFSRST4 = 1u;
00934       break;
00935     case ClkResetMfs5:
00936       FM0P_PCG->MRST0_f.MFSRST5 = 1u;
00937       break;
00938     case ClkResetMfs6:
00939       FM0P_PCG->MRST0_f.MFSRST6 = 1u;
00940       break;
00941     case ClkResetMfs7:
00942       FM0P_PCG->MRST0_f.MFSRST7 = 1u;
00943       break;
00944     case ClkResetMfs8:
00945       FM0P_PCG->MRST0_f.MFSRST8 = 1u;
00946       break;
00947     case ClkResetMfs9:
00948       FM0P_PCG->MRST0_f.MFSRST9 = 1u;
00949       break;
00950     case ClkResetMfs10:
00951       FM0P_PCG->MRST0_f.MFSRST10 = 1u;
00952       break;
00953     case ClkResetMfs11:
00954       FM0P_PCG->MRST0_f.MFSRST11 = 1u;
00955       break;
00956     case ClkResetMfs12:
00957       FM0P_PCG->MRST0_f.MFSRST12 = 1u;
00958       break;
00959     case ClkResetMfs13:
00960       FM0P_PCG->MRST0_f.MFSRST13 = 1u;
00961       break;
00962     case ClkResetMfs14:
00963       FM0P_PCG->MRST0_f.MFSRST14 = 1u;
00964       break;
00965     case ClkResetMfs15:
00966       FM0P_PCG->MRST0_f.MFSRST15 = 1u;
00967       break;
00968     case ClkResetQprc0:
00969       FM0P_PCG->MRST1_f.QDURST0 = 1u;
00970       break;
00971     case ClkResetQprc1:
00972       FM0P_PCG->MRST1_f.QDURST1 = 1u;
00973       break;
00974     case ClkResetQprc2:
00975       FM0P_PCG->MRST1_f.QDURST2 = 1u;
00976       break;
00977     case ClkResetQprc3:
00978       FM0P_PCG->MRST1_f.QDURST3 = 1u;
00979       break;
00980     case ClkResetMft0:
00981       FM0P_PCG->MRST1_f.MFTRST0 = 1u;
00982       break;
00983     case ClkResetMft1:
00984       FM0P_PCG->MRST1_f.MFTRST1 = 1u;
00985       break;
00986     case ClkResetMft2:
00987       FM0P_PCG->MRST1_f.MFTRST2 = 1u;
00988       break;
00989     case ClkResetMft3:
00990       FM0P_PCG->MRST1_f.MFTRST3 = 1u;
00991       break;
00992     case ClkResetBt0:
00993       FM0P_PCG->MRST1_f.BTMRST0 = 1u;
00994       break;
00995     case ClkResetBt4:
00996       FM0P_PCG->MRST1_f.BTMRST1 = 1u;
00997       break;
00998     case ClkResetBt8:
00999       FM0P_PCG->MRST1_f.BTMRST2 = 1u;
01000       break;
01001     case ClkResetBt12:
01002       FM0P_PCG->MRST1_f.BTMRST3 = 1u;
01003       break;
01004     case ClkResetCan0:
01005       FM0P_PCG->MRST2_f.CANRST0 = 1u;
01006       break;
01007     case ClkResetCan1:
01008       FM0P_PCG->MRST2_f.CANRST1 = 1u;
01009       break;
01010     default:
01011       return ErrorInvalidParameter;
01012   }
01013   
01014   return Ok;
01015 } // Clk_PeripheralSetReset
01016 
01030 en_result_t Clk_PeripheralClearReset(en_clk_reset_peripheral_t enPeripheral)
01031 {
01032   switch (enPeripheral)
01033   {
01034     case ClkResetDma:
01035       FM0P_PCG->MRST0_f.DMARST = 0u;
01036       break;
01037     case ClkResetAdc0:
01038       FM0P_PCG->MRST0_f.ADCRST0 = 0u;
01039       break;
01040     case ClkResetAdc1:
01041       FM0P_PCG->MRST0_f.ADCRST1 = 0u;
01042       break;
01043     case ClkResetAdc2:
01044       FM0P_PCG->MRST0_f.ADCRST2 = 0u;
01045       break;
01046     case ClkResetAdc3:
01047       FM0P_PCG->MRST0_f.ADCRST3 = 0u;
01048       break;
01049     case ClkResetMfs0:
01050       FM0P_PCG->MRST0_f.MFSRST0 = 0u;
01051       break;
01052     case ClkResetMfs1:
01053       FM0P_PCG->MRST0_f.MFSRST1 = 0u;
01054       break;
01055     case ClkResetMfs2:
01056       FM0P_PCG->MRST0_f.MFSRST2 = 0u;
01057       break;
01058     case ClkResetMfs3:
01059       FM0P_PCG->MRST0_f.MFSRST3 = 0u;
01060       break;
01061     case ClkResetMfs4:
01062       FM0P_PCG->MRST0_f.MFSRST4 = 0u;
01063       break;
01064     case ClkResetMfs5:
01065       FM0P_PCG->MRST0_f.MFSRST5 = 0u;
01066       break;
01067     case ClkResetMfs6:
01068       FM0P_PCG->MRST0_f.MFSRST6 = 0u;
01069       break;
01070     case ClkResetMfs7:
01071       FM0P_PCG->MRST0_f.MFSRST7 = 0u;
01072       break;
01073     case ClkResetMfs8:
01074       FM0P_PCG->MRST0_f.MFSRST8 = 0u;
01075       break;
01076     case ClkResetMfs9:
01077       FM0P_PCG->MRST0_f.MFSRST9 = 0u;
01078       break;
01079     case ClkResetMfs10:
01080       FM0P_PCG->MRST0_f.MFSRST10 = 0u;
01081       break;
01082     case ClkResetMfs11:
01083       FM0P_PCG->MRST0_f.MFSRST11 = 0u;
01084       break;
01085     case ClkResetMfs12:
01086       FM0P_PCG->MRST0_f.MFSRST12 = 0u;
01087       break;
01088     case ClkResetMfs13:
01089       FM0P_PCG->MRST0_f.MFSRST13 = 0u;
01090       break;
01091     case ClkResetMfs14:
01092       FM0P_PCG->MRST0_f.MFSRST14 = 0u;
01093       break;
01094     case ClkResetMfs15:
01095       FM0P_PCG->MRST0_f.MFSRST15 = 0u;
01096       break;
01097     case ClkResetQprc0:
01098       FM0P_PCG->MRST1_f.QDURST0 = 0u;
01099       break;
01100     case ClkResetQprc1:
01101       FM0P_PCG->MRST1_f.QDURST1 = 0u;
01102       break;
01103     case ClkResetQprc2:
01104       FM0P_PCG->MRST1_f.QDURST2 = 0u;
01105       break;
01106     case ClkResetQprc3:
01107       FM0P_PCG->MRST1_f.QDURST3 = 0u;
01108       break;
01109     case ClkResetMft0:
01110       FM0P_PCG->MRST1_f.MFTRST0 = 0u;
01111       break;
01112     case ClkResetMft1:
01113       FM0P_PCG->MRST1_f.MFTRST1 = 0u;
01114       break;
01115     case ClkResetMft2:
01116       FM0P_PCG->MRST1_f.MFTRST2 = 0u;
01117       break;
01118     case ClkResetMft3:
01119       FM0P_PCG->MRST1_f.MFTRST3 = 0u;
01120       break;
01121     case ClkResetBt0:
01122       FM0P_PCG->MRST1_f.BTMRST0 = 0u;
01123       break;
01124     case ClkResetBt4:
01125       FM0P_PCG->MRST1_f.BTMRST1 = 0u;
01126       break;
01127     case ClkResetBt8:
01128       FM0P_PCG->MRST1_f.BTMRST2 = 0u;
01129       break;
01130     case ClkResetBt12:
01131       FM0P_PCG->MRST1_f.BTMRST3 = 0u;
01132       break;
01133     case ClkResetCan0:
01134       FM0P_PCG->MRST2_f.CANRST0 = 0u;
01135       break;
01136     case ClkResetCan1:
01137       FM0P_PCG->MRST2_f.CANRST1 = 0u;
01138       break;
01139     default:
01140       return ErrorInvalidParameter;
01141   }
01142   
01143   return Ok;
01144 } // Clk_PeripheralClearReset
01145        
01147 
01148 #endif // #if (defined(PDL_PERIPHERAL_ENABLE_CLK))
01149 
01150 /******************************************************************************/
01151 /* EOF (not truncated)                                                        */
01152 /******************************************************************************/