==============================================================================================
                              PDL Project for FM0+ Family 
==============================================================================================

Copyright (C) 2013 Spansion LLC. All Rights Reserved. 

This software is owned and published by: 
Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").

BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 
BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.

This software contains source code for use with Spansion 
components. This software is licensed by Spansion to be adapted only 
for use in systems utilizing Spansion components. Spansion shall not be 
responsible for misuse or illegal use of this software for devices not 
supported herein.  Spansion is providing this software "AS IS" and will 
not be responsible for issues arising from incorrect user implementation 
of the software.  

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at all times.                                                                                         
                                                                                                                                                   
==========================================================================
 
History
Date        Ver   IAR    ARM    Description
2014-01-22  0.1   6.50   4.70   first version (alpha release)
2014-02-26  0.2   6.50   4.70   All drivers and simple examples available
2014-03-17  0.3   6.50   4.70   Add advance examples in ADC/LPM/MFS/RTC
2014-03-31  1.0   6.50   4.70   Add the utility drivers

==========================================================================

PDL (Peripheral Driver Library)

This library contains driver modules for the following peripherals and
resources:

- ADC   Analog Digital Cionverter
- BT    Base Time
- CAN   Controller Area Network
- CLK   Clock Module
- CR    High-CR trimming
- CSV   Clock supervisor
- DMA   Direc Memory Access
- DT    Dual Timer
- EXINT External Interrupt
- Flash Main Flash operation
- GPIO  General Purpose Inoput/Output Ports (only header file)
- LPM   Low Power Modes
- LVD   Low Voltage Detection
- MFS   Multi Function Serial Interface
- MFT   Multi Function Timer
- QPRC  Quad Decoder and Position/Revolution Counter
- RESET Reset Cause Register
- RTC   Real Time Clock
- UID   Unique ID
- WC    Watch Counter
- WDG   Watch Dog Timer

For almost all peripheral modules there is several example code available.
These examples are located in the example folder and its sub folders (see
below at the PDL's directory tree).


The following examples are available:
-------------------------------------

- ADC
  - adc_scan_multich_irq_bt       ADC multi-channels scan sample with interrupt mode triggered by base timer
  - adc_scan_multich_irq_sw       ADC multi-channels scan conversion with usage of interrupt callback triggered by software
  - adc_scan_multich_irq_mft      ADC multi-channels scan conversion with usage of interrupt callback triggered by MFT
  - adc_scan_multich_polling_sw   ADC multi-channels scan conversion with polling for conversion finish triggered by software
  - adc_scan_onech_irq_sw         ADC single-channel scan sample with interrupt mode triggered by software
  - adc_scan_onech_polling_sw     ADC single-channel scan conversion with polling for conversion finish triggered by software
  - adc_scan_dma                  ADC scan conversion using DMA
  - adc_prio_irq_sw               ADC priority conversion with usage of interrupt callback triggered by software
  - adc_prio_polling_sw           ADC priority conversion with polling for finished conversion triggered by software
  - adc_range_compare             ADC result range comparison function implementation
  - adc_result_compare            ADC result value comparison function implementation  
                                
- BT
  - bt_iomode        Base Timer IO modes demonstration             
  - bt_ppg           Base Timer configured as Programmable Pulse Generator
  - bt_pwc           Base Timer configured as Pulse Width Counter
  - bt_pwm           Base Timer configured as Pulse With Modulator
  - bt_rt            Base Timer configured as Reload Timer 

- CLK  
  - clk_gating       Clock gating setting 
  - clk_init         User clock initialization
                     
- CR
  - cr_trimming      CR trimming procedure demonstration   

- CSV
  - csv_reset        CSV reset demonstration when main/sub clock frequency is abnormal
  - fcs_int          FCS interrupt demonstration when main clock frequency is abnormal
  - fcs_reset        CSV reset demonstration when main clock frequency is abnormal

- DMA                
  - dma_software     The DMA perform a sotware block transfer

- DT                 
  - dt_unuse_int     Dual Timer configured as periodic mode for ch.0 and one-shot mode for ch.1 with usage interruption callback
  - dt_use_int       Dual Timer configured as periodic mode for ch.0 and one-shot mode for ch.1 with polling for interruption

- EXINT
  - exint_simple     Simple external interrupt occurence demonstration
  - exint_dma        USing external interrupt to trigger DMA transfer

- Flash
  - main_flash_test  Main Flash operation test

- GPIO               
  - gpio_set        Simple GPIO pin setting
  - fgpio_set       Simple Fast GPIO pin setting

- LPM
  - lpm_sleep       MCU is set to sleep mode, EXINT3 wakes up MCU
  - lpm_rtc_mode    MCU is set to RTC mode, RTC timer interrupt wakes up MCU
 
- LVD                
  - lvd_int          Interrupt occurs when Low voltage is detected
  - lvd_polling      Low voltage detection using interrupt flag polling

- MFS 
  - UART
    - uart_interrupt      UART communication between 2 channels with interrupt enabled
    - uart_polling        UART communication between 2 channels with interrupt flag polling
    - uart_dma            UART communication between 2 channels with interrupt enabled using DMA
    - uart_fifo_interrupt UART communication between 2 channels with interrupt enabled using FIFO
  - CSIO
    - csio_interrupt      CSIO communication between 2 channels(one for Master, the other for Slave) with interrupt enabled
    - csio_polling        CSIO communication between 2 channels(one for Master, the other for Slave) with interrupt flag polling
    - csio_dma            CSIO communication between 2 channels(one for Master, the other for Slave) with interrupt enabled using DMA
    - csio_fifo_interrupt CSIO communication between 2 channels(one for Master, the other for Slave) with interrupt enabled using FIFO
    - csio_trig_by_sync_timer CSIO communication between 2 channels(one for Master, the other for Slave) with interrupt enabled triggered by Serial timer
    - csio_using_cs           CSIO communication between 2 channels(one for Master, the other for Slave) with interrupt enabled and CS pin enabled 
    - csio_flash              Using CSIO to access to SPI Flash
  - i2c
    - i2c_polling
      - i2c_master_polling   I2C channel acts as I2C master with TX/RX completion polling, which communicates with the slave "i2c_slave_polling"
      - i2c_slave_polling    I2C channel acts as I2C slave with TX/RX completion polling, which communicates with the slave "i2c_master_polling"
    - i2c_eeprom             Access to EEPROm with I2C interface with interrupt mode or polling mode
                    
- MFT                
  - FRT              
    - frt_int        Free-run Timer function with usage of zero/peak match interrupt callback
    - frt_polling    Free-run Timer function with polling for zero/peak match
  - ICU              
    - icu_int        Input Captuer Unit function with usage of interrupt callback
    - icu_polling    Input Captuer Unit function with polling for capture completion
  - OCU
    - ocu_ch_linked  Perform 2 change linked mode of Output Compare Unit   
    - ocu_ch_single  Perform 1-change/low-active/high-active mode of Output Compare Unit
  - WFG
    - wfg_nzcl_dtif_dttix_trig Perform DTIF interrupt triggered DTTIX
    - wfg_nzcl_dtif_sw_trig    Perform DTIF interrupt triggered software
    - wfg_ppg_dead_timer_mode  Perform PPG-dead timer mode of Waveform Generator Unit
    - wfg_rt_dead_timer_mode   Perform RT-dead timer mode of Waveform Generator Unit 
    - wfg_rt_ppg_mode          Perform RT-PPG mode of Waveform Generator Unit
    - wfg_through_mode         Perform through mode of Waveform Generator Unit
    - wfg_timer_ppg_mode       Perform Timer-PPG mode of Waveform Generator Unit

- QPRC
  - qprc_pc_directional       Perform Count mode with direction (mode 3) of Position Counter  
  - qprc_pc_updown            Perform Up/down count mode (mode 1) of Position Counter
  - qprc_pc_phase_diff        Perform Phase different count mode (mode 2) of Position Counter 
  - qprc_rc_pc_ofuf_trig      Perform Revolution Counter mode 2 (triggered by Position Counter)
  - qprc_rc_zin_pcofuf_trig   Perform Revolution Counter mode 3 (triggered by ZIN or Position Counter)
  - qprc_rc_zin_trig          Perform Revolution Counter mode 1 (triggered by ZIN)

- RTC
  - rtc_count        Usage of time counting and alarm interruption for RTC
  - rtc_timer        Usage of timer interruption for RTC
  - rtc_calibration  Usage of calibration function for RTC    
 
- UID
  - uid_read          Several methods to read the Unique ID

- WC
  - wc_int            Watch Counter function with usage of interrupt callback
  - wc_polling        Watch Counter function with polling for interrupt occurrence

- WDG
  - hwwdg             Usage of hardware watchdog
  - swwdg
    - swwdg_normal    Usage of normal mode for software watchdog
    - swwdg_normal    Usage of window mode for software watchdog

Usage of example code:
----------------------

Each example code consists of a 'main.c' and a 'pdl_user.h' module.
The main module contains the example code, where 'pdl_user.h'
contains all necessary settings and definitions for the example
itself.
To use and compile an example, just copy these two modules
to the 'template/source' folder, overwriting the modules located
there. The overwritten modules have backups in the 'template/
source/backup' folder for recovery.
All adjustments for IAR Workbench and ARM/KEIL uVision IDE are
done in the template project and will fit to the example code.
Follow the explanations and advices in the main.c module's
description in the comment lines at the top.


Clock settings used in system_mbxxx.c/.h:
-----------------------------------------
Crystal:  4 MHz
HCLK:    40 MHz
PCLK0:   40 MHz
PCLK1:   40 MHz


Folder structure of the PDL project:
------------------------------------

mb9bfxxx_pdl-vxy
 !
 +-- common
 !
 +-- example
 !    !
 !    +-- adc
 !    !    ! 
 !    !    +-- adc_dma
 !    !    +-- adc_irq
 !    !    +-- adc_polling
 !    !   ...
 !    !
 !    +-- bt
 !    !    !
 !   ...   +-- ...
 !
 +-- libray
 !    !
 !    +-- driver
 !    !    !
 !    !    +-- adc
 !    !    +-- bt
 !    !    +-- ...
 !    !   ...
 !    !
 !    +-- utility
 !    !    !
 !    !    +-- at24cxx
 !    !    +-- s25fl127s
 !    !   ...
 !    !
 !    +-- midware
 !
 +-- template
       !
       +-- ARM
       !    !
       !    +-- output
       !         !
       !         +-- debug
       !         *-- release
       !
       +-- IAR
       !    !
       !    +-- config
       !    !    !
       !    !    +-- flashloader
       !    !
       !    +-- debug
       !    !    !
       !    !    +-- exe
       !    !    +-- list
       !    !    +-- obj
       !    !
       !    +-- release 
       !    !    !
       !    !    +-- exe
       !    !    +-- list
       !    !    +-- obj
       !    !
       !    +-- settings
       !
       +-- source
