| PDL for FM0+ Version1.0 Peripheral Driverl Library for FM0+

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C:/pdl_v10/library/driver/clk/clk.h
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    00001 /*******************************************************************************
    00002 * Copyright (C) 2013 Spansion LLC. All Rights Reserved.
    00003 *
    00004 * This software is owned and published by:
    00005 * Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
    00006 *
    00007 * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
    00008 * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
    00009 *
    00010 * This software contains source code for use with Spansion
    00011 * components. This software is licensed by Spansion to be adapted only
    00012 * for use in systems utilizing Spansion components. Spansion shall not be
    00013 * responsible for misuse or illegal use of this software for devices not
    00014 * supported herein.  Spansion is providing this software "AS IS" and will
    00015 * not be responsible for issues arising from incorrect user implementation
    00016 * of the software.
    00017 *
    00018 * SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
    00019 * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
    00020 * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
    00021 * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
    00022 * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
    00023 * WARRANTY OF NONINFRINGEMENT.
    00024 * SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
    00025 * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
    00026 * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
    00027 * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
    00028 * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
    00029 * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
    00030 * SAVINGS OR PROFITS,
    00031 * EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    00032 * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
    00033 * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
    00034 * FROM, THE SOFTWARE.
    00035 *
    00036 * This software may be replicated in part or whole for the licensed use,
    00037 * with the restriction that this Disclaimer and Copyright notice must be
    00038 * included with each copy of this software, whether used in part or whole,
    00039 * at all times.
    00040 */
    00041 /******************************************************************************/
    00051 #ifndef __CLK_H__
    00052 #define __CLK_H__
    00053
    00054 /******************************************************************************/
    00055 /* Include files                                                              */
    00056 /******************************************************************************/
    00057 #include "mcu.h"
    00058 #include "pdl_user.h"
    00059
    00060 #if (defined(PDL_PERIPHERAL_CLK_ACTIVE))
    00061
    00062 /* C binding of definitions if building with C++ compiler */
    00063 #ifdef __cplusplus
    00064 extern "C"
    00065 {
    00066 #endif
    00067
    00121
    00122 /******************************************************************************
    00123  * Global type definitions
    00124  ******************************************************************************/
    00125 // PLL Input Clock Select (PINC) Bit Position
    00126 #define FM0P_PSW_TMR_PINC_BITPOS 0x10u
    00127
    00128 // Interrupt enable bit positions in INT_ENR
    00129 #define FM0P_INT_ENR_PCSE_BITPOS 0x04u
    00130 #define FM0P_INT_ENR_SCSE_BITPOS 0x02u
    00131 #define FM0P_INT_ENR_MCSE_BITPOS 0x01u
    00132
    00133 // Interrupt status bit positions in INT_STR
    00134 #define FM0P_INT_STR_PCSI_BITPOS 0x04u
    00135 #define FM0P_INT_STR_SCSI_BITPOS 0x02u
    00136 #define FM0P_INT_STR_MCSI_BITPOS 0x01u
    00137
    00138 // Interrupt clear bit positions in INT_CLR
    00139 #define FM0P_INT_CLR_PCSC_BITPOS 0x04u
    00140 #define FM0P_INT_CLR_SCSC_BITPOS 0x02u
    00141 #define FM0P_INT_CLR_MCSC_BITPOS 0x01u
    00142
    00155 typedef enum en_clk_source
    00156 {
    00157   ClkMain = 0,
    00158   ClkSub  = 1,
    00159   ClkHsCr = 2,
    00160   ClkLsCr = 3,
    00161   ClkPll  = 4,
    00162   ClkHsCrPll = 5
    00163 } en_clk_source_t;
    00164
    00171 typedef enum en_clk_baseclkdiv
    00172 {
    00173   BaseClkDiv1  = 0,
    00174   BaseClkDiv2  = 1,
    00175   BaseClkDiv3  = 2,
    00176   BaseClkDiv4  = 3,
    00177   BaseClkDiv6  = 4,
    00178   BaseClkDiv8  = 5,
    00179   BaseClkDiv16 = 6,
    00180   BaseClkErr   = 7
    00181 } en_clk_baseclkdiv_t;
    00182
    00189 typedef enum en_clk_apb0div
    00190 {
    00191   Apb0Div1  = 0,
    00192   Apb0Div2  = 1,
    00193   Apb0Div4  = 2,
    00194   Apb0Div8  = 3
    00195 } en_clk_apb0div_t;
    00196
    00203 typedef enum en_clk_apb1div
    00204 {
    00205   Apb1Div1  = 0,
    00206   Apb1Div2  = 1,
    00207   Apb1Div4  = 2,
    00208   Apb1Div8  = 3
    00209 } en_clk_apb1div_t;
    00210
    00217 typedef enum en_clk_scowaittime
    00218 {
    00219   ScoWaitExp10  =  0,
    00220   ScoWaitExp11  =  1,
    00221   ScoWaitExp12  =  2,
    00222   ScoWaitExp13  =  3,
    00223   ScoWaitExp14  =  4,
    00224   ScoWaitExp15  =  5,
    00225   ScoWaitExp16  =  6,
    00226   ScoWaitExp17  =  7,
    00227   ScoWaitExp18  =  8,
    00228   ScoWaitExp19  =  9,
    00229   ScoWaitExp20  = 10,
    00230   ScoWaitExp21  = 11,
    00231   ScoWaitErr    = 12
    00232 } en_clk_scowaittime_t;
    00233
    00240 typedef enum en_clk_mcowaittime
    00241 {
    00242   McoWaitExp11   = 0,
    00243   McoWaitExp15   = 1,
    00244   McoWaitExp16   = 2,
    00245   McoWaitExp17   = 3,
    00246   McoWaitExp18   = 4,
    00247   McoWaitExp19   = 5,
    00248   McoWaitExp110  = 6,
    00249   McoWaitExp111  = 7,
    00250   McoWaitExp112  = 8,
    00251   McoWaitExp113  = 9,
    00252   McoWaitExp114  = 10,
    00253   McoWaitExp115  = 11,
    00254   McoWaitExp117  = 12,
    00255   McoWaitExp119  = 13,
    00256   McoWaitExp121  = 14,
    00257   McoWaitExp123  = 15
    00258 } en_clk_mcowaittime_t;
    00259
    00266 typedef enum en_clk_pllowaittime
    00267 {
    00268   PlloWaitExp19   = 0,
    00269   PlloWaitExp110  = 1,
    00270   PlloWaitExp111  = 2,
    00271   PlloWaitExp112  = 3,
    00272   PlloWaitExp113  = 4,
    00273   PlloWaitExp114  = 5,
    00274   PlloWaitExp115  = 6,
    00275   PlloWaitExp116  = 7
    00276 } en_clk_pllowaittime_t;
    00277
    00288 typedef enum en_clk_pll_src
    00289 {
    00290   PllSrcClkMo = 0,
    00291   PllSrcClkHc = 123
    00292 } en_clk_pll_src_t;
    00293
    00298 #if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON)
    00299 typedef struct stc_clk_intern_data
    00300 {
    00301   func_ptr_t            pfnPllStabCb;
    00302   func_ptr_t            pfnScoStabCb;
    00303   func_ptr_t            pfnMcoStabCb;
    00304 } stc_clk_intern_data_t ;
    00305 #endif
    00306
    00311 typedef enum en_clk_gate_peripheral
    00312 {
    00313   ClkGateGpio   = 0,
    00314   ClkGateDma    = 2,
    00315   ClkGateAdc0   = 3,
    00316   ClkGateAdc1   = 4,
    00317   ClkGateAdc2   = 5,
    00318   ClkGateAdc3   = 6,
    00319   ClkGateMfs0   = 7,
    00320   ClkGateMfs1   = 8,
    00321   ClkGateMfs2   = 9,
    00322   ClkGateMfs3   = 10,
    00323   ClkGateMfs4   = 11,
    00324   ClkGateMfs5   = 12,
    00325   ClkGateMfs6   = 13,
    00326   ClkGateMfs7   = 14,
    00327   ClkGateMfs8   = 15,
    00328   ClkGateMfs9   = 16,
    00329   ClkGateMfs10  = 17,
    00330   ClkGateMfs11  = 18,
    00331   ClkGateMfs12  = 19,
    00332   ClkGateMfs13  = 20,
    00333   ClkGateMfs14  = 21,
    00334   ClkGateMfs15  = 22,
    00335   ClkGateQprc0  = 23,
    00336   ClkGateQprc1  = 24,
    00337   ClkGateQprc2  = 25,
    00338   ClkGateQprc3  = 26,
    00339   ClkGateMft0   = 27,
    00340   ClkGateMft1   = 28,
    00341   ClkGateMft2   = 29,
    00342   ClkGateMft3   = 30,
    00343   ClkGateBt0    = 31,
    00344   ClkGateBt4    = 32,
    00345   ClkGateBt8    = 33,
    00346   ClkGateBt12   = 34,
    00347   ClkGateCan0   = 36,
    00348   ClkGateCan1   = 37,
    00349 } en_clk_gate_peripheral_t;
    00350
    00355 typedef enum en_clk_reset_peripheral
    00356 {
    00357   ClkResetDma    = 2,
    00358   ClkResetAdc0   = 3,
    00359   ClkResetAdc1   = 4,
    00360   ClkResetAdc2   = 5,
    00361   ClkResetAdc3   = 6,
    00362   ClkResetMfs0   = 7,
    00363   ClkResetMfs1   = 8,
    00364   ClkResetMfs2   = 9,
    00365   ClkResetMfs3   = 10,
    00366   ClkResetMfs4   = 11,
    00367   ClkResetMfs5   = 12,
    00368   ClkResetMfs6   = 13,
    00369   ClkResetMfs7   = 14,
    00370   ClkResetMfs8   = 15,
    00371   ClkResetMfs9   = 16,
    00372   ClkResetMfs10  = 17,
    00373   ClkResetMfs11  = 18,
    00374   ClkResetMfs12  = 19,
    00375   ClkResetMfs13  = 20,
    00376   ClkResetMfs14  = 21,
    00377   ClkResetMfs15  = 22,
    00378   ClkResetQprc0  = 23,
    00379   ClkResetQprc1  = 24,
    00380   ClkResetQprc2  = 25,
    00381   ClkResetQprc3  = 26,
    00382   ClkResetMft0   = 27,
    00383   ClkResetMft1   = 28,
    00384   ClkResetMft2   = 29,
    00385   ClkResetMft3   = 30,
    00386   ClkResetBt0    = 31,
    00387   ClkResetBt4    = 32,
    00388   ClkResetBt8    = 33,
    00389   ClkResetBt12   = 34,
    00390   ClkResetSdIf   = 35,
    00391   ClkResetCan0   = 36,
    00392   ClkResetCan1   = 37,
    00393 } en_clk_reset_peripheral_t;
    00394
    00401 typedef struct stc_clk_config
    00402 {
    00403   en_clk_baseclkdiv_t   enBaseClkDiv;
    00404   en_clk_apb0div_t      enAPB0Div;
    00405   en_clk_apb1div_t      enAPB1Div;
    00406   boolean_t             bAPB1Disable;
    00407   en_clk_mcowaittime_t  enMCOWaitTime;
    00408   en_clk_scowaittime_t  enSCOWaitTime;
    00409   en_clk_pllowaittime_t enPLLOWaitTime;
    00410   uint8_t               u8PllK;
    00411   uint8_t               u8PllM;
    00412   uint8_t               u8PllN;
    00413 #if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON)
    00414   boolean_t             bPllIrq;
    00415   boolean_t             bMcoIrq;
    00416   boolean_t             bScoIrq;
    00417   func_ptr_t            pfnPllStabCb;
    00418   func_ptr_t            pfnMcoStabCb;
    00419   func_ptr_t            pfnScoStabCb;
    00420 #endif
    00421 } stc_clk_config_t;
    00422
    00423 /******************************************************************************/
    00424 /* Global variable definitions ('extern')                                     */
    00425 /******************************************************************************/
    00426 #if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON)
    00427 extern stc_clk_intern_data_t stcClkInternData;
    00428 #endif
    00429
    00430 /******************************************************************************/
    00431 /* Global function prototypes (definition in C source)                        */
    00432 /******************************************************************************/
    00433
    00434 #if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON)
    00435 void Clk_IrqHandler(void) ;
    00436 #endif
    00437 /* Set clock divider, wait time, interrupt */
    00438 en_result_t Clk_Init(stc_clk_config_t* pstcClk) ;
    00439 /* Clock enable/disable */
    00440 en_result_t Clk_EnableHscr(boolean_t bBlock);
    00441 en_result_t Clk_DisableHscr(void);
    00442 en_result_t Clk_EnableMainClock(boolean_t bBlock);
    00443 en_result_t Clk_DisableMainClock(void);
    00444 en_result_t Clk_EnableSubClock(boolean_t bBlock);
    00445 en_result_t Clk_DisableSubClock(void);
    00446 en_result_t Clk_EnablePllClock(boolean_t bBlock);
    00447 en_result_t Clk_DisablePllClock(void);
    00448 /* Set the source clock */
    00449 en_result_t Clk_SetSource(en_clk_source_t enSource);
    00450 /* Peripheral clock enable/disable/status read */
    00451 en_result_t Clk_PeripheralClockEnable(en_clk_gate_peripheral_t enPeripheral) ;
    00452 en_result_t Clk_PeripheralClockDisable(en_clk_gate_peripheral_t enPeripheral) ;
    00453 boolean_t Clk_PeripheralGetClockState(en_clk_gate_peripheral_t enPeripheral) ;
    00454 /* Peripheral set reset/release reset */
    00455 en_result_t Clk_PeripheralSetReset(en_clk_reset_peripheral_t enPeripheral) ;
    00456 en_result_t Clk_PeripheralClearReset(en_clk_reset_peripheral_t enPeripheral) ;
    00457
    00459
    00460 #ifdef __cplusplus
    00461 }
    00462 #endif
    00463
    00464 #endif // #if (defined(PDL_PERIPHERAL_CLK_ACTIVE))
    00465
    00466 #endif /* __CLK_H__ */
    00467 /******************************************************************************/
    00468 /* EOF (not truncated)                                                        */
    00469 /******************************************************************************/